VLSI architecture for motion vector quantization

Wen Jyi Hwang*, Chien Min Ou, Wen Ming Lu, Chun Fu Lin


研究成果: 雜誌貢獻期刊論文同行評審

1 引文 斯高帕斯(Scopus)


This paper present a novel VLSI architecture for the block-matching operations based on the motion vector quantizers (MVQs). Since the distribution of the check point locations of the MVQ is irregular, the usual VLSI architectures for regular block-matching processes may not be effective for the hardware implementation of the MVQ. Our architecture solves this problem by adopting a scheme capable of performing both sequential and parallel block-matching processes. For the check points having close locations, their block-matching processes are performed sequentially to reduce both the I/O rate and the clock cycle. On the other hand, we perform the parallel block-matching processes for the check points which are widely separated so that the clock cycle can be reduced while retaining the I/O rate. Because of the flexibility for the sequential and parallel selection, our architecture requires less clock cycle and I/O rate for the MVQ hardware implementation as compared with other existing architectures.

頁(從 - 到)237-242
期刊IEEE Transactions on Consumer Electronics
出版狀態已發佈 - 2003 2月

ASJC Scopus subject areas

  • 媒體技術
  • 電氣與電子工程


深入研究「VLSI architecture for motion vector quantization」主題。共同形成了獨特的指紋。