VLSI architecture for fast memetic vector quantizer design on reconfigurable hardware

Sheng Kai Weng, Chien Min Ou, Wen Jyi Hwang*

*此作品的通信作者

研究成果: 書貢獻/報告類型會議論文篇章

摘要

A novel hardware architecture for memetic vector quantizer (VQ) design is presented in this paper. The architecture uses steady-state genetic algorithm (GA) for global search, and C-means algorithm for local refinement. It adopts a shift register based circuit for accelerating mutation and crossover operations for steady state GA operations. It also uses a pipeline architecture for the hardware implementation of C-means algorithm. The proposed architecture has been embedded in a softcore CPU for physical performance measurement. Experimental results show that the proposed architecture is an effective alternative for VQ optimization attaining both high performance and low computational time.

原文英語
主出版物標題Algorithms and Architectures for Parallel Processing - 9th International Conference, ICA3PP 2009, Proceedings
頁面513-524
頁數12
DOIs
出版狀態已發佈 - 2009 九月 21
事件9th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2009 - Taipei, 臺灣
持續時間: 2009 六月 82009 六月 11

出版系列

名字Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
5574 LNCS
ISSN(列印)0302-9743
ISSN(電子)1611-3349

其他

其他9th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2009
國家/地區臺灣
城市Taipei
期間2009/06/082009/06/11

ASJC Scopus subject areas

  • 理論電腦科學
  • 電腦科學(全部)

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