Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology

Chun Yu Lin; Pin Hsin Chang; Rong Kun Chang; Ming Dou Ker; Wen Tai Wang

doi:10.1109/IPFA.2015.7224380

Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology

Chun Yu Lin, Pin Hsin Chang, Rong Kun Chang, Ming Dou Ker, Wen Tai Wang

電機工程學系

研究成果: 書貢獻/報告類型 › 會議論文篇章

2 引文斯高帕斯（Scopus）

摘要

A vertical silicon-controlled rectifier (SCR) structure utilizing ESD implantation layer was proposed and implemented in nanoscale CMOS technology. Compared with the traditional SCR structure, the proposed structure has lower trigger voltage and high enough ESD protection capability. Therefore, the proposed structure was suitable for ESD protection in nanoscale CMOS process.

原文	英語
主出版物標題	Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	255-258
頁數	4
ISBN（電子）	9781479999286, 9781479999286
DOIs	https://doi.org/10.1109/IPFA.2015.7224380
出版狀態	已發佈 - 2015 8月 25
事件	22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015 - Hsinchu, 臺灣持續時間: 2015 6月 29 → 2015 7月 2

出版系列

名字	Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
卷	2015-August

其他

其他	22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015
國家/地區	臺灣
城市	Hsinchu
期間	2015/06/29 → 2015/07/02

ASJC Scopus subject areas

電氣與電子工程

存取文件

10.1109/IPFA.2015.7224380

其它文件與鏈接

引用此

Lin, C. Y., Chang, P. H., Chang, R. K., Ker, M. D., & Wang, W. T. (2015). Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology. 於 Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015 (頁 255-258). 文章 7224380 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA; 卷 2015-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IPFA.2015.7224380

Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology. / Lin, Chun Yu; Chang, Pin Hsin; Chang, Rong Kun 等.
Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 255-258 7224380 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA; 卷 2015-August).

研究成果: 書貢獻/報告類型 › 會議論文篇章

Lin, CY, Chang, PH, Chang, RK, Ker, MD & Wang, WT 2015, Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology. 於 Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015., 7224380, Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, 卷 2015-August, Institute of Electrical and Electronics Engineers Inc., 頁 255-258, 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015, Hsinchu, 臺灣, 2015/06/29. https://doi.org/10.1109/IPFA.2015.7224380

Lin CY, Chang PH, Chang RK, Ker MD, Wang WT. Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology. 於 Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 255-258. 7224380. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). doi: 10.1109/IPFA.2015.7224380

Lin, Chun Yu ; Chang, Pin Hsin ; Chang, Rong Kun 等. / Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology. Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 頁 255-258 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

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abstract = "A vertical silicon-controlled rectifier (SCR) structure utilizing ESD implantation layer was proposed and implemented in nanoscale CMOS technology. Compared with the traditional SCR structure, the proposed structure has lower trigger voltage and high enough ESD protection capability. Therefore, the proposed structure was suitable for ESD protection in nanoscale CMOS process.",

author = "Lin, {Chun Yu} and Chang, {Pin Hsin} and Chang, {Rong Kun} and Ker, {Ming Dou} and Wang, {Wen Tai}",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015 ; Conference date: 29-06-2015 Through 02-07-2015",

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AB - A vertical silicon-controlled rectifier (SCR) structure utilizing ESD implantation layer was proposed and implemented in nanoscale CMOS technology. Compared with the traditional SCR structure, the proposed structure has lower trigger voltage and high enough ESD protection capability. Therefore, the proposed structure was suitable for ESD protection in nanoscale CMOS process.

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Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology

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