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Using binary resistors to achieve multilevel resistive switching in multilayer NiO/Pt nanowire arrays

  • Yen Chun Huang
  • , Po Yuan Chen
  • , Kuo Feng Huang
  • , Tzu Chi Chuang
  • , Hsiu Hau Lin
  • , Tsung Shune Chin
  • , Ru Shi Liu
  • , Yann Wen Lan
  • , Chii Dong Chen
  • , Chih Huang Lai*
  • *此作品的通信作者

研究成果: 雜誌貢獻期刊論文同行評審

23   連結會在新分頁中打開 引文 斯高帕斯(Scopus)

摘要

Reliable multilevel resistive switching in nanoscale cells is desirable for the wide adoption of resistive random access memory as the next-generation nonvolatile memory. We designed NiO-based cells in arrays of multilayered NiO/Pt nanowires to explore multilevel memory effects. Nonpolar resistive switching reproducibly occurs with significantly reduced switching voltages, narrow switching voltage distributions and a robust multilevel memory effect. A high resistance ratio (∼105) between the highand low-resistance states in nanoscale cells enables stable multilevels that can be induced easily by a series of pulsed voltage. The existence of intermediate resistance states in NiO/Pt nanowire arrays can be well explained by the binary-resistor model combined with energy perturbations induced by the pulse voltage. We also verified that the conduction mechanism in multilayered NiO/Pt nanowires is dominated by the hopping of holes. Our bottom-up approach and proposed mechanism explain the controllable multilevel memory effect and facilitate sound device design to encourage their universal adoption.

原文英語
文章編號81
期刊NPG Asia Materials
6
發行號2
DOIs
出版狀態已發佈 - 2014 2月
對外發佈

ASJC Scopus subject areas

  • 建模與模擬
  • 一般材料科學
  • 凝聚態物理學

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