摘要
We report a low-temperature InP p-MOS with a high capacitance density of 2.7 μF/ cm2 , low leakage current of 0.77 A/cm2 at 1 V and tight current distribution. The high-density and low-leakage InP MOS was achieved by using high- κ TiLaO dielectric and ultra-thin SiO2 buffer layer with a thickness of less than 0.5 nm. The obtained EOT can be aggressively scaled down to < 1 nm through the use of stacked TiLaO/SiO2 dielectric, which has the potential for the future application of high mobility III-V CMOS devices.
原文 | 英語 |
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頁(從 - 到) | 2810-2813 |
頁數 | 4 |
期刊 | Journal of Nanoscience and Nanotechnology |
卷 | 15 |
發行號 | 4 |
DOIs | |
出版狀態 | 已發佈 - 2015 1月 1 |
ASJC Scopus subject areas
- 生物工程
- 一般化學
- 生物醫學工程
- 一般材料科學
- 凝聚態物理學