The guideline on designing face-tunneling FET for large-scale-device applications in IoT

E. R. Hsieh*, J. W. Lee, M. H. Lee, Steve S. Chung

*此作品的通信作者

研究成果: 書貢獻/報告類型會議論文篇章

摘要

A thorough understanding on how to design and to manufacture a face-tunneling TFET (f-TFET) has been provided. By taking advantage of an area-tunneling, in comparison to conventional point-tunneling FET, f-TFET can be enhanced in its current. This work shows I0 of f-TFET with one-order magnitude In enhancement than that of point-TFET(control), and the longer the gate length is, the higher the becomes. However, from experimental results, S.S. of f-TFET is a little worse than that of control and shows strong dependency on temperature because of dominance of trap-assisted tunneling. To understand how traps affect Ion of f-TFET, the charge-pumping measurement is utilized to examine trap distributions in the tunneling region. The results show that the channel/source interfacial traps degrade the performance of f-TFET, however, with careful treatment of the epi-process of f-TFET, this device with face-tunneling shows great potential for future IoT applications.

原文英語
主出版物標題2017 Silicon Nanoelectronics Workshop, SNW 2017
發行者Institute of Electrical and Electronics Engineers Inc.
頁面3-4
頁數2
ISBN(電子)9784863486478
DOIs
出版狀態已發佈 - 2017 十二月 29
事件22nd Silicon Nanoelectronics Workshop, SNW 2017 - Kyoto, 日本
持續時間: 2017 六月 42017 六月 5

出版系列

名字2017 Silicon Nanoelectronics Workshop, SNW 2017
2017-January

其他

其他22nd Silicon Nanoelectronics Workshop, SNW 2017
國家/地區日本
城市Kyoto
期間2017/06/042017/06/05

ASJC Scopus subject areas

  • 電氣與電子工程
  • 電子、光磁材料

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