The guideline on designing a high performance nc mosfet by matching the gate capacitance and mobility enhancement

Y. C. Luo, F. L. Li, E. R. Hsieh, C. H. Liu, Steve S. Chung, T. P. Chen, S. A. Huang, T. J. Chen, Osbert Chenz

研究成果: 書貢獻/報告類型會議貢獻

摘要

In this paper, to provide a guideline of designing a high-performance NCFET, we explored not only the capacitance matching between ferroelectric HZO MIM and MOSFET but also how effective mobility is affected by HZO dipoles. For capacitance matching, we observe a 50x enhancement of overall gate capacitance triggered by NC effect, while, however, it generated an adverse degradation of the mobility. This mobility degradation is induced by the remote scattering from the ferroelectric HZO dipoles. Fortunately, if suitable polarization can be formed to align the HZO dipoles, the effects of remote scattering can be mitigated. From a trade-off between gate capacitance and the mobility, an NCFET with desirable characteristics can be achieved. Besides, we showed that improved SS is possible when the derivative of the voltage across the ferroelectric MIM is negative and is corresponding to the release of energy from the ferroelectric MIM which boosts SS.

原文英語
主出版物標題2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781728109428
DOIs
出版狀態已發佈 - 2019 四月
事件2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019 - Hsinchu, 臺灣
持續時間: 2019 四月 222019 四月 25

出版系列

名字2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019

會議

會議2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019
國家臺灣
城市Hsinchu
期間19/4/2219/4/25

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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    Luo, Y. C., Li, F. L., Hsieh, E. R., Liu, C. H., Chung, S. S., Chen, T. P., Huang, S. A., Chen, T. J., & Chenz, O. (2019). The guideline on designing a high performance nc mosfet by matching the gate capacitance and mobility enhancement. 於 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019 [8804688] (2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-TSA.2019.8804688