The FPGA implementation of 128-bits AES algorithm based on four 32-bits parallel operation

Chi-Wu Huang, Chi Jeng Chang, Mao Yuan Lin, Hung Yun Tai

研究成果: 書貢獻/報告類型會議貢獻

13 引文 斯高帕斯(Scopus)

摘要

A 32-bit AES implementation is proposed in small Xilinx FPGA Chip (Spartan-3 XC3S200). It uses 148 slices, 11 Block RAMs (BRAMs) and achieves a throughput of 647 Mega bits per second ( Mbps) at 278 MHz working frequency. It achieve 3 times improvement in throughput and 3.4 times increase to the best known similar design in throughput per area and 8% smaller in slices area. An 128-bit AES implementation in FPGA (Virtex-II XC2VP20) by parallel operations of four above 32-bit AES is also presented. Comparison to state-of-art AES cores indicates that the proposed folded designed achieves 4780 Mbps and 410 slices, which outperformed the most recent works by 200% in throughput and requires 20% less reconfigurable area, which results over 250% improvement in throughput/slice metric.

原文英語
主出版物標題Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007
頁面462-464
頁數3
DOIs
出版狀態已發佈 - 2007 十二月 1
事件1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007 - Chengdu, 中国
持續時間: 2007 十一月 12007 十一月 3

出版系列

名字Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007

其他

其他1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007
國家中国
城市Chengdu
期間07/11/107/11/3

    指紋

ASJC Scopus subject areas

  • Computer Science(all)
  • Economics, Econometrics and Finance (miscellaneous)

引用此

Huang, C-W., Chang, C. J., Lin, M. Y., & Tai, H. Y. (2007). The FPGA implementation of 128-bits AES algorithm based on four 32-bits parallel operation. 於 Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007 (頁 462-464). [4402734] (Proceedings of the 1st International Symposium on Data, Privacy, and E-Commerce, ISDPE 2007). https://doi.org/10.1109/ISDPE.2007.128