The fabrication and the reliability of poly-Si MOSFETs using ultra-thin high-K/metal-gate stack

M. H. Lee*, K. J. Chen

*此作品的通信作者

研究成果: 雜誌貢獻期刊論文同行評審

1 引文 斯高帕斯(Scopus)

摘要

Poly-Si MOSFETs using a gate stack composed of ultra-thin HfSiOx and TiN are shown, and they are compatible with a monolithic three-dimensional integrated circuit (3D-ICs) process with the highest thermal budget of 700 °C. The poly-Si MOSFETs were studied for fabrication process temperatures with parasitic resistance, effective gate length, and grain boundary trap density. The short-channel effect with VT (threshold voltage), subthreshold swing (SS), and drain-induced barrier lowering (DIBL) was also compared at 650 °C and 700 °C. For stress reliability of both hot carrier and PBTI, the short-channel devices showed more stability in V T than the long-channel devices due to less grain boundary scattering. This study promotes the ultra-thin high-K/metal gate poly-Si MOSFET as a candidate for future monolithic 3D-ICs and silicon-on-glass (SOG) applications.

原文英語
頁(從 - 到)244-247
頁數4
期刊Solid-State Electronics
79
DOIs
出版狀態已發佈 - 2013 一月

ASJC Scopus subject areas

  • 電子、光磁材料
  • 凝聚態物理學
  • 電氣與電子工程
  • 材料化學

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