@inproceedings{ee9730f9e53e45938ec23aee3b058643,
title = "The enhancement of MOSFET electric performance through strain engineering by refilled sige as Source and Drain",
abstract = "Mismatched lattice constants between SiGe and silicon can cause the strain making the mobility improved. SiGe are grown underneath the channel apparently to form global strain over the whole devices, while Source/Drain refilled with SiGe would squeeze or pull up the devices uni-axially. The ID-V G characteristics curves and the maximum trans-conductance (g m) using strain engineering are observed to be superior to the baseline. Nevertheless, the breakdown voltages with strain engineering no longer enjoy as robustly as ones without.",
keywords = "SiGe-Refilled Source/Drain, Strained Engineering",
author = "Yang, {Hsin Chia} and Li, {Chao Wang} and Liao, {Wen Shiang} and Du, {Chong Kuan} and Wang, {Mu Chun} and Yang, {Jie Min} and Lian, {Chun Wei} and Liu, {Chuan Hsi}",
year = "2013",
doi = "10.1109/INEC.2013.6466014",
language = "English",
isbn = "9781467348416",
series = "Proceedings - Winter Simulation Conference",
pages = "251--253",
booktitle = "Proceedings of the 2013 IEEE 5th International Nanoelectronics Conference, INEC 2013",
note = "2013 IEEE 5th International Nanoelectronics Conference, INEC 2013 ; Conference date: 02-01-2013 Through 04-01-2013",
}