TY - GEN
T1 - The Design of High Performance Si/SiGe-Based Tunneling FET
T2 - 2018 IEEE International Conference on Electron Devices and Solid State Circuits, EDSSC 2018
AU - Chung, Steve S.
AU - Hsieh, E. R.
AU - Zhao, Y. B.
AU - Lee, J. W.
AU - Lee, M. H.
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/10/9
Y1 - 2018/10/9
N2 - The strategy and solutions in the design of tunneling FET for low voltage/power applications will be addressed in this paper. First, the concept of a face-tunneling scheme to provide a sufficient improvement over the conventional point tunneling has been justified by an experiment. By taking advantage of an area-tunneling, in comparison to conventional point-tunneling FET, face-tunneling FET (f-TFET) can be enhanced in its Ion current. This work shows Ion of f-TFET with one-order magnitude Ion enhancement than that of point-TFET(control), and the longer the gate length is, the higher the Ion becomes. However, from experimental results, S.S. of f-TFET is a little worse than that of control. This can be better improved by careful treatment of a special design epi-channel, Next, further improvement of the TFET performance has been proposed by a further design of an improved epitaxial SiGe-based channel structure. The design is based on a raised-drain structure with further improvement on the Ion current and much lower S. S. down to 28mV/dec.
AB - The strategy and solutions in the design of tunneling FET for low voltage/power applications will be addressed in this paper. First, the concept of a face-tunneling scheme to provide a sufficient improvement over the conventional point tunneling has been justified by an experiment. By taking advantage of an area-tunneling, in comparison to conventional point-tunneling FET, face-tunneling FET (f-TFET) can be enhanced in its Ion current. This work shows Ion of f-TFET with one-order magnitude Ion enhancement than that of point-TFET(control), and the longer the gate length is, the higher the Ion becomes. However, from experimental results, S.S. of f-TFET is a little worse than that of control. This can be better improved by careful treatment of a special design epi-channel, Next, further improvement of the TFET performance has been proposed by a further design of an improved epitaxial SiGe-based channel structure. The design is based on a raised-drain structure with further improvement on the Ion current and much lower S. S. down to 28mV/dec.
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U2 - 10.1109/EDSSC.2018.8487104
DO - 10.1109/EDSSC.2018.8487104
M3 - Conference contribution
AN - SCOPUS:85056336754
T3 - 2018 IEEE International Conference on Electron Devices and Solid State Circuits, EDSSC 2018
BT - 2018 IEEE International Conference on Electron Devices and Solid State Circuits, EDSSC 2018
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 6 June 2018 through 8 June 2018
ER -