The Design of High Performance Si/SiGe-Based Tunneling FET: Strategies and Solutions

Steve S. Chung, E. R. Hsieh, Y. B. Zhao, J. W. Lee, M. H. Lee

研究成果: 書貢獻/報告類型會議論文篇章

摘要

The strategy and solutions in the design of tunneling FET for low voltage/power applications will be addressed in this paper. First, the concept of a face-tunneling scheme to provide a sufficient improvement over the conventional point tunneling has been justified by an experiment. By taking advantage of an area-tunneling, in comparison to conventional point-tunneling FET, face-tunneling FET (f-TFET) can be enhanced in its Ion current. This work shows Ion of f-TFET with one-order magnitude Ion enhancement than that of point-TFET(control), and the longer the gate length is, the higher the Ion becomes. However, from experimental results, S.S. of f-TFET is a little worse than that of control. This can be better improved by careful treatment of a special design epi-channel, Next, further improvement of the TFET performance has been proposed by a further design of an improved epitaxial SiGe-based channel structure. The design is based on a raised-drain structure with further improvement on the Ion current and much lower S. S. down to 28mV/dec.

原文英語
主出版物標題2018 IEEE International Conference on Electron Devices and Solid State Circuits, EDSSC 2018
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781538662342
DOIs
出版狀態已發佈 - 2018 十月 9
事件2018 IEEE International Conference on Electron Devices and Solid State Circuits, EDSSC 2018 - Shenzhen, 中国
持續時間: 2018 六月 62018 六月 8

出版系列

名字2018 IEEE International Conference on Electron Devices and Solid State Circuits, EDSSC 2018

會議

會議2018 IEEE International Conference on Electron Devices and Solid State Circuits, EDSSC 2018
國家/地區中国
城市Shenzhen
期間2018/06/062018/06/08

ASJC Scopus subject areas

  • 電氣與電子工程
  • 電子、光磁材料

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