Test structure on SCR device in waffle layout for RF ESD protection

Ming Dou Ker; Chun Yu Lin

doi:10.1109/ICMTS.2007.374482

Test structure on SCR device in waffle layout for RF ESD protection

Ming Dou Ker^*, Chun Yu Lin

^*此作品的通信作者

研究成果: 書貢獻/報告類型 › 會議論文篇章

5 引文斯高帕斯（Scopus）

摘要

With the highest ESD level in a smallest layout area, SCR device was used as effective on-chip ESD protection device in CMOS technology. In this paper, a waffle layout test structure of SCR is proposed to investigate the current spreading efficiency for ESD protection. The SCR in waffle layout structure has smaller parasitic capacitance under the same ESD robustness. With smaller parasitic capacitance, the degradation on RF circuit performance due to on-chip ESD protection device can be reduced. The proposed waffle SCR is suitable for on-chip ESD protection in RF applications.

原文	英語
主出版物標題	2007 IEEE International Conference on Microelectronic Test Structures, ICMTS - Conference Proceedings
頁面	196-199
頁數	4
DOIs	https://doi.org/10.1109/ICMTS.2007.374482
出版狀態	已發佈 - 2007
對外發佈	是
事件	2007 IEEE International Conference on Microelectronic Test Structures, ICMTS '07 - Bunkyo-ku, 日本持續時間: 2007 3月 19 → 2007 3月 22

出版系列

名字	IEEE International Conference on Microelectronic Test Structures

其他

其他	2007 IEEE International Conference on Microelectronic Test Structures, ICMTS '07
國家/地區	日本
城市	Bunkyo-ku
期間	2007/03/19 → 2007/03/22

ASJC Scopus subject areas

電氣與電子工程

存取文件

10.1109/ICMTS.2007.374482

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引用此

Ker, MD & Lin, CY 2007, Test structure on SCR device in waffle layout for RF ESD protection. 於 2007 IEEE International Conference on Microelectronic Test Structures, ICMTS - Conference Proceedings., 4252432, IEEE International Conference on Microelectronic Test Structures, 頁 196-199, 2007 IEEE International Conference on Microelectronic Test Structures, ICMTS '07, Bunkyo-ku, 日本, 2007/03/19. https://doi.org/10.1109/ICMTS.2007.374482

@inproceedings{eac982dcfab849fc90c77a2cf1bdbfcc,

title = "Test structure on SCR device in waffle layout for RF ESD protection",

abstract = "With the highest ESD level in a smallest layout area, SCR device was used as effective on-chip ESD protection device in CMOS technology. In this paper, a waffle layout test structure of SCR is proposed to investigate the current spreading efficiency for ESD protection. The SCR in waffle layout structure has smaller parasitic capacitance under the same ESD robustness. With smaller parasitic capacitance, the degradation on RF circuit performance due to on-chip ESD protection device can be reduced. The proposed waffle SCR is suitable for on-chip ESD protection in RF applications.",

keywords = "Electrostatic discharges (ESD), Radio-frequency integrated circuit (RF IC), Silicon-controlled rectifier (SCR)",

author = "Ker, {Ming Dou} and Lin, {Chun Yu}",

year = "2007",

doi = "10.1109/ICMTS.2007.374482",

language = "English",

isbn = "142440780X",

series = "IEEE International Conference on Microelectronic Test Structures",

pages = "196--199",

booktitle = "2007 IEEE International Conference on Microelectronic Test Structures, ICMTS - Conference Proceedings",

note = "2007 IEEE International Conference on Microelectronic Test Structures, ICMTS '07 ; Conference date: 19-03-2007 Through 22-03-2007",

}

TY - GEN

T1 - Test structure on SCR device in waffle layout for RF ESD protection

AU - Ker, Ming Dou

AU - Lin, Chun Yu

PY - 2007

Y1 - 2007

N2 - With the highest ESD level in a smallest layout area, SCR device was used as effective on-chip ESD protection device in CMOS technology. In this paper, a waffle layout test structure of SCR is proposed to investigate the current spreading efficiency for ESD protection. The SCR in waffle layout structure has smaller parasitic capacitance under the same ESD robustness. With smaller parasitic capacitance, the degradation on RF circuit performance due to on-chip ESD protection device can be reduced. The proposed waffle SCR is suitable for on-chip ESD protection in RF applications.

AB - With the highest ESD level in a smallest layout area, SCR device was used as effective on-chip ESD protection device in CMOS technology. In this paper, a waffle layout test structure of SCR is proposed to investigate the current spreading efficiency for ESD protection. The SCR in waffle layout structure has smaller parasitic capacitance under the same ESD robustness. With smaller parasitic capacitance, the degradation on RF circuit performance due to on-chip ESD protection device can be reduced. The proposed waffle SCR is suitable for on-chip ESD protection in RF applications.

KW - Electrostatic discharges (ESD)

KW - Radio-frequency integrated circuit (RF IC)

KW - Silicon-controlled rectifier (SCR)

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DO - 10.1109/ICMTS.2007.374482

M3 - Conference contribution

AN - SCOPUS:34548828536

SN - 142440780X

SN - 9781424407804

T3 - IEEE International Conference on Microelectronic Test Structures

SP - 196

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BT - 2007 IEEE International Conference on Microelectronic Test Structures, ICMTS - Conference Proceedings

T2 - 2007 IEEE International Conference on Microelectronic Test Structures, ICMTS '07

Y2 - 19 March 2007 through 22 March 2007

ER -

Test structure on SCR device in waffle layout for RF ESD protection

摘要

出版系列

其他

ASJC Scopus subject areas

存取文件

其它文件與鏈接

指紋

引用此