@inproceedings{df5d67c367b944fe84124dcf93358bcb,
title = "Superlattice HfO2-ZrO2based Ferro-Stack HfZrO2FeFETs: Homogeneous-Domain Merits Ultra-Low Error, Low Programming Voltage 4 V and Robust Endurance 109cycles for Multibit NVM",
abstract = "Superlattice (SL) HfO2-ZrO2 with physical thickness of 5 nm and low phase fraction ratio 0.101:1 of monoclinic-phase (m-phase) to orthorhombic-phase (o-phase) investigated by geometrical phase analysis (GPA) is demonstrated. The homogeneous and congruous of SL-HfZrO2 (HZO) with sufficient ferroelectric-domain is integrated as ferro-stack FeFETs for multibit NVM with low |VPG/ER| = 4 V, ultra-low error rate = 7.5×10-16, record high 2-bit endurance for 109 cycles, and stable data retention > 104 s. The device-to-device (D2D) variation of nanoscale 3D FeFETs is also improved with the proposed SL-HZO. The superlattice technique for FE-HZO is a promising concept with elevating the coherence of domain access due to high o-phase toward emerging memory applications.",
author = "Liao, {C. Y.} and Lou, {Z. F.} and Lin, {C. Y.} and A. Senapati and R. Karmakar and Hsiang, {K. Y.} and Li, {Z. X.} and Ray, {W. C.} and Lee, {J. Y.} and Chen, {P. H.} and Chang, {F. S.} and Tseng, {H. H.} and Wang, {C. C.} and Tsai, {J. H.} and Tang, {Y. T.} and Chang, {S. T.} and Liu, {C. W.} and S. Maikap and Lee, {M. H.}",
note = "Funding Information: ACKNOWLEDGMENT This work was supported in part by the Ministry of Science and Technology (MOST) under Grants 111-2218-E-A49-016-MBK, 111-2221-E-003-031-MY3, 111-2221-E-182-063, 110-2622-8-002-014. Processes were supported by Taiwan Semiconductor Research Institute (TSRI) & Nano Facility Center (NFC), Taiwan. REFERENCES [1] S. L. Weeks et al., ACS Appl. Mater. Interfaces, 9, 13440-13447, 2017. [2] S. Migita et al., APEX, 14, 2021, 051006. [3] S. S. Cheema et al., Nature, 604, 65-71, 2022. [4] M. H. Park et al., Appl. Phys. Rev., 6, 2018, 041403. [5] C.-Y. Liao et al., IEEE EDL, 42(4), 617-620, 2021. [6] T. Ali et al., in IEDM, 2019, 665-668. [7] Z.-F. Lou et al., in VLSI-TSA, 2022, 1-2. [8] S. Riedel et al., AIP Adv., 6, 2016, 095123. [9] M. H. Park et al., APL, 104(7), 2014, 072901. [10] H. J. Kim et al., APL, 105(19), 2014,192903.[11]H.Leeetal.,ACSAppl.Mater.Interfaces,13,36499-36506,2021. [12] S. Stemmer et al, JVST B, 22(2), 791-800, 2004. [13] K. Ni et al., in IEDM, 150-153, 2019. [14] Q. Luo et al., Nat. Commun., 11, 2020, 1391. [15] T. Y. Lee et al., ACS Appl. Mater. Interfaces, 11, 3141-3149, 2019. [16] V. Gaddam et al., IEEE TED,67(2),745-750,2020.[17]H.Mulaosmanovicetal.,ACSAppl.Mater.Interfaces, 9(4), 3792-3798, 2017. [18] M. H. Lee et al., in IEDM, 735-738, 2018. Publisher Copyright: {\textcopyright} 2022 IEEE.; 2022 International Electron Devices Meeting, IEDM 2022 ; Conference date: 03-12-2022 Through 07-12-2022",
year = "2022",
doi = "10.1109/IEDM45625.2022.10019369",
language = "English",
series = "Technical Digest - International Electron Devices Meeting, IEDM",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "3661--3664",
booktitle = "2022 International Electron Devices Meeting, IEDM 2022",
}