Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology

Chun Yu Lin; Ming Dou Ker; Pin Hsin Chang; Wen Tai Wang

doi:10.1109/NMDC.2015.7439250

Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology

Chun Yu Lin, Ming Dou Ker, Pin Hsin Chang, Wen Tai Wang

電機工程學系

研究成果: 書貢獻/報告類型 › 會議論文篇章

9 引文斯高帕斯（Scopus）

摘要

To protect the IC chips against the electrostatic discharge (ESD) damages in 28nm high-k metal-gate (HKMG) CMOS technology, the ESD protection consideration was studied in this work. The ESD design window was found to be within 1V and 5.1V in 28nm HKMG CMOS technology. An ESD protection device of PMOS with embedded silicon-controlled rectifier (SCR) was investigated to be suitable for ESD protection in such narrow ESD design window.

原文	英語
主出版物標題	2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015
發行者	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子）	9781467393621
DOIs	https://doi.org/10.1109/NMDC.2015.7439250
出版狀態	已發佈 - 2016 3月 22
事件	10th IEEE Nanotechnology Materials and Devices Conference, NMDC 2015 - Anchorage, 美国持續時間: 2015 9月 12 → 2015 9月 16

出版系列

名字	2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015

其他

其他	10th IEEE Nanotechnology Materials and Devices Conference, NMDC 2015
國家/地區	美国
城市	Anchorage
期間	2015/09/12 → 2015/09/16

ASJC Scopus subject areas

電氣與電子工程
電子、光磁材料

存取文件

10.1109/NMDC.2015.7439250

其它文件與鏈接

引用此

Lin, C. Y., Ker, M. D., Chang, P. H., & Wang, W. T. (2016). Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology. 於 2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015 文章 7439250 (2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/NMDC.2015.7439250

Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology. / Lin, Chun Yu; Ker, Ming Dou; Chang, Pin Hsin 等.
2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015. Institute of Electrical and Electronics Engineers Inc., 2016. 7439250 (2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015).

研究成果: 書貢獻/報告類型 › 會議論文篇章

Lin, CY, Ker, MD, Chang, PH & Wang, WT 2016, Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology. 於 2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015., 7439250, 2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015, Institute of Electrical and Electronics Engineers Inc., 10th IEEE Nanotechnology Materials and Devices Conference, NMDC 2015, Anchorage, 美国, 2015/09/12. https://doi.org/10.1109/NMDC.2015.7439250

Lin CY, Ker MD, Chang PH, Wang WT. Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology. 於 2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015. Institute of Electrical and Electronics Engineers Inc. 2016. 7439250. (2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015). doi: 10.1109/NMDC.2015.7439250

Lin, Chun Yu ; Ker, Ming Dou ; Chang, Pin Hsin 等. / Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology. 2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015. Institute of Electrical and Electronics Engineers Inc., 2016. (2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015).

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title = "Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology",

abstract = "To protect the IC chips against the electrostatic discharge (ESD) damages in 28nm high-k metal-gate (HKMG) CMOS technology, the ESD protection consideration was studied in this work. The ESD design window was found to be within 1V and 5.1V in 28nm HKMG CMOS technology. An ESD protection device of PMOS with embedded silicon-controlled rectifier (SCR) was investigated to be suitable for ESD protection in such narrow ESD design window.",

keywords = "CMOS, electrostatic discharge (ESD), high-k metal-gate (HKMG), silicon-controlled rectifier (SCR)",

author = "Lin, {Chun Yu} and Ker, {Ming Dou} and Chang, {Pin Hsin} and Wang, {Wen Tai}",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 10th IEEE Nanotechnology Materials and Devices Conference, NMDC 2015 ; Conference date: 12-09-2015 Through 16-09-2015",

year = "2016",

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doi = "10.1109/NMDC.2015.7439250",

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T1 - Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology

AU - Lin, Chun Yu

AU - Ker, Ming Dou

AU - Chang, Pin Hsin

AU - Wang, Wen Tai

PY - 2016/3/22

Y1 - 2016/3/22

N2 - To protect the IC chips against the electrostatic discharge (ESD) damages in 28nm high-k metal-gate (HKMG) CMOS technology, the ESD protection consideration was studied in this work. The ESD design window was found to be within 1V and 5.1V in 28nm HKMG CMOS technology. An ESD protection device of PMOS with embedded silicon-controlled rectifier (SCR) was investigated to be suitable for ESD protection in such narrow ESD design window.

AB - To protect the IC chips against the electrostatic discharge (ESD) damages in 28nm high-k metal-gate (HKMG) CMOS technology, the ESD protection consideration was studied in this work. The ESD design window was found to be within 1V and 5.1V in 28nm HKMG CMOS technology. An ESD protection device of PMOS with embedded silicon-controlled rectifier (SCR) was investigated to be suitable for ESD protection in such narrow ESD design window.

KW - CMOS

KW - electrostatic discharge (ESD)

KW - high-k metal-gate (HKMG)

KW - silicon-controlled rectifier (SCR)

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BT - 2015 IEEE Nanotechnology Materials and Devices Conference, NMDC 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 10th IEEE Nanotechnology Materials and Devices Conference, NMDC 2015

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Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology

摘要

出版系列

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ASJC Scopus subject areas

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