SRAM-based computation in memory architecture to realize single command of add-multiply operation and multifunction

Chua Chin Wang, Chia Yi Huang, Chia Hung Yeh

研究成果: 書貢獻/報告類型會議論文篇章

摘要

This paper presents a computation in memory (CIM) architecture and circuit design featured with single command to execute addition, signed multiplication, and multi-function to resolve poor computation throughput caused by von Neumann bottleneck. The proposed CIM takes advantage of 2T-Switch circuit which needs only 2 switches to select the required computation units such that the area on silicon is reduced. RCAM (ripple carry adder and multiply) unit realized with full swing gate diffusion input (FS-GDI) in a single-ended disturb-free 7T SRAM further reduces the power consumption and active circuit area. Auto-switching write-back circuit consisting of BL auto-switching circuit, Data switching circuit, and WL auto-switching circuit facilitates the automatic restore of addition and multiplication to designated memory addresses. The proposed CIM is realized using 40-nm CMOS process to demonstrated 12.18/28.19 fJ/bit normalized write/read energy at 100 MHz system clock rate.

原文英語
主出版物標題2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781728192017
DOIs
出版狀態已發佈 - 2021
事件53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Daegu, 大韓民國
持續時間: 2021 五月 222021 五月 28

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
2021-May
ISSN(列印)0271-4310

會議

會議53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021
國家/地區大韓民國
城市Daegu
期間2021/05/222021/05/28

ASJC Scopus subject areas

  • 電氣與電子工程

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