Single-electron transistor using self-aligned sidewall spacer gates on silicon-on-insulator nanowire

S. F. Hu, Y. C. Wu, C. L. Sung, C. Y. Chang, T. Y. Huang

研究成果: 書貢獻/報告類型會議貢獻

2 引文 斯高帕斯(Scopus)

摘要

A dual-gate-controlled single-electron transistor was fabricated by using self-aligned polysilicon sidewall spacer gates on a silicon-on-insulator nanowire. The quantum dot formed by the electric field effect of the dual-gate structure was miniaturized to smaller than the state-of-the-art feature size, through a combination of electron beam lithography, oxidation and polysilicon sidewall spacer gate formation processes. The device shows typical MOSFET I-V characteristics at room temperature. However, the Coulomb gap and Coulomb oscillations are clearly observed at 4 K.

原文英語
主出版物標題2003 3rd IEEE Conference on Nanotechnology, IEEE-NANO 2003 - Proceedings
發行者IEEE Computer Society
頁面573-576
頁數4
ISBN(電子)0780379764
DOIs
出版狀態已發佈 - 2003 一月 1
事件2003 3rd IEEE Conference on Nanotechnology, IEEE-NANO 2003 - San Francisco, 美国
持續時間: 2003 八月 122003 八月 14

出版系列

名字Proceedings of the IEEE Conference on Nanotechnology
2
ISSN(列印)1944-9399
ISSN(電子)1944-9380

其他

其他2003 3rd IEEE Conference on Nanotechnology, IEEE-NANO 2003
國家美国
城市San Francisco
期間03/8/1203/8/14

ASJC Scopus subject areas

  • Bioengineering
  • Electrical and Electronic Engineering
  • Materials Chemistry
  • Condensed Matter Physics

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  • 引用此

    Hu, S. F., Wu, Y. C., Sung, C. L., Chang, C. Y., & Huang, T. Y. (2003). Single-electron transistor using self-aligned sidewall spacer gates on silicon-on-insulator nanowire. 於 2003 3rd IEEE Conference on Nanotechnology, IEEE-NANO 2003 - Proceedings (頁 573-576). [1230975] (Proceedings of the IEEE Conference on Nanotechnology; 卷 2). IEEE Computer Society. https://doi.org/10.1109/NANO.2003.1230975