Shift-or circuit for efficient network intrusion detection pattern matching

Huang Chun Roan, Wen-Jyi Hwang*, Chia Tien Dan Lo

*此作品的通信作者

研究成果: 書貢獻/報告類型會議論文篇章

11 引文 斯高帕斯(Scopus)

摘要

This paper introduces a novel FPGA-based signature match co-processor architecture serving as the core of a hardwarebased network intrusion detection system (NIDS). The signature match co-processor architecture is based on the shift-or algorithm. The architecture is comprised of simple shift registers, or-gates, and ROMs where patterns are stored. As compared with related work, experimental results show that the proposed work achieves higher throughput and less hardware resource in the FPGA implementations of NIDS systems.

原文英語
主出版物標題Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL
頁面785-790
頁數6
DOIs
出版狀態已發佈 - 2006 十二月 1
事件2006 International Conference on Field Programmable Logic and Applications, FPL - Madrid, 西班牙
持續時間: 2006 八月 282006 八月 30

出版系列

名字Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL

其他

其他2006 International Conference on Field Programmable Logic and Applications, FPL
國家/地區西班牙
城市Madrid
期間2006/08/282006/08/30

ASJC Scopus subject areas

  • 計算機理論與數學
  • 電氣與電子工程

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