Settling studies of underfill particles for flip-chip solder interconnections

In view of the flip-chip on board packaging method, an underfill encapsulant material is dispensed along one or two adjacent sides of the chip. The capillary force then draws the underfill beneath the chip to fill the gap between the integrated circuit (IC) chip and substrate. These shear stresses are imposed on the solder interconnections owing to a significant mismatch of coefficient of thermal expansion (CTE) between the IC chip and substrate. Hence, this underfill is required to specifically harmonize the CTE value of the solder for minimization of the stresses caused by the thermal inconsistency between the IC chip and substrate. This paper aims to conduct the micromechanical analysis using the Eshelby equivalence inclusions principle and Mori-Tankaka's average stress field concept for investigating the equivalence thermolelastic of underfill filler particles. In calculations, the finite element method (FEM) software ANSYS is used to simulate the inhomogeneity of underfill fillers, such as settling of filler particles, for appraising the reliability of flip chip solder interconnections. We further probed if the reliability of flip chip solder interconnections could be influenced by the predicted volume fractions of underfill fillers.