Robust ESD protection design for 40-GB/s transceiver in 65-Nm CMOS process

Chun Yu Lin, Li Wei Chu, Ming Dou Ker

研究成果: 雜誌貢獻文章

4 引文 斯高帕斯(Scopus)

摘要

To protect a 40-Gb/s transceiver from electrostatic discharge (ESD) damages, a robust ESD protection design has been proposed and realized in a 65-nm CMOS process. In this paper, diodes are used for ESD protection and inductors are used for high-speed performance fine tuning. Experimental results of the test circuits have been successfully verified, including high-speed performances and ESD robustness. The proposed design has been further applied to a 40-Gb/s current-mode logic (CML) buffer. Verified in silicon chip, the 40-Gb/s CML buffer with the proposed design can achieve good high-speed performance and high ESD robustness.

原文英語
文章編號6588898
頁(從 - 到)3625-3631
頁數7
期刊IEEE Transactions on Electron Devices
60
發行號11
DOIs
出版狀態已發佈 - 2013 九月 9

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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