In this letter, an on-chip electrostatic discharge (ESD) protection device was proposed for highspeed I/O interface circuits. A resistor-triggered siliconcontrolled rectifier device with improved performance was designed and investigated in a nanoscale CMOS process. As verified in a 0.18-μm CMOS process, the proposed design exhibits a lower clamping voltage and low enough overshoot voltage during ESD stress conditions, and lower parasitic capacitance and low enough leakage current during normal circuit operating conditions. Therefore, the proposed design is suitable for ESD protection of high-speed circuits in low-voltage CMOS processes.
|頁（從 - 到）||712-715|
|期刊||IEEE Electron Device Letters|
|出版狀態||已發佈 - 2017 6月|
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