Quantum well nanopillar transistors

Shu Fen Hu, Chin Lung Sung

研究成果: 書貢獻/報告類型會議貢獻

摘要

We have fabricated vertical quantum well nanopillar transistors that consist of a vertical stack of coupled asymmetric quantum wells in a poly-silicon/ silicon nitride multilayer nano-pillars configuration with each well having a unique size. The devices consist of resonant tunneling in the poly-silicon/ silicon nitride stacked pillar material system surrounded by a Schottky gate. The gate electrode surrounds half side of a silicon pillar island, and the channel region exists at all the pillar silicon island. Current-voltage measurements at room temperature show prominent quantum effects due to electron resonance tunneling with side-gate. Accordingly, the vertical transistor offers high-shrinkage feature. By using the occupied area of the ULSI can be shrunk to 10% of that using conventional planar transistor. The small-occupied area leads to the small capacitance and the small load resistance, resulting in high speed and low power operation.

原文英語
主出版物標題Transistor Scaling-Methods, Materials and Modeling
發行者Materials Research Society
頁面85-92
頁數8
ISBN(列印)1558998691, 9781558998698
DOIs
出版狀態已發佈 - 2006
事件2006 MRS Spring Meeting - San Francisco, CA, 美国
持續時間: 2006 四月 182006 四月 19

出版系列

名字Materials Research Society Symposium Proceedings
913
ISSN(列印)0272-9172

其他

其他2006 MRS Spring Meeting
國家美国
城市San Francisco, CA
期間06/4/1806/4/19

ASJC Scopus subject areas

  • Materials Science(all)
  • Condensed Matter Physics
  • Mechanics of Materials
  • Mechanical Engineering

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