Prospects for ferroelectric HfZrOx FETs with experimentally CET=0.98nm, SSfor=42mV/dec, SSrev=28mV/dec, switch-off <0.2V, and hysteresis-free strategies

M. H. Lee; P. G. Chen; C. Liu; K. Y. Chu; C. C. Cheng; M. J. Xie; S. N. Liu; J. W. Lee; S. J. Huang; M. H. Liao; M. Tang; K. S. Li; M. C. Chen

doi:10.1109/IEDM.2015.7409759

Prospects for ferroelectric HfZrOx FETs with experimentally CET=0.98nm, SS_for=42mV/dec, SS_rev=28mV/dec, switch-off <0.2V, and hysteresis-free strategies

M. H. Lee
, P. G. Chen
, C. Liu
, K. Y. Chu
, C. C. Cheng
, M. J. Xie
, S. N. Liu
, J. W. Lee
, S. J. Huang
, M. H. Liao
, M. Tang
, K. S. Li
, M. C. Chen

光電工程研究所暨學士學位學程

研究成果: 書貢獻/報告類型 › 會議論文篇章

96 引文斯高帕斯（Scopus）

摘要

Ferroelectric HfZrOx (FE-HZO) FETs is experimentally demonstrated with 0.98nm CET (capacitance equivalent thickness), small hysteresis window V_T (threshold voltage) shift < 0.1V, SS_for = 42mV/dec, SS_rev = 28mV/dec, and switch-off < 0.2V. The optimum ALD process leads single monolayer SiO_x for IL (interfacial layer) and low gate leakage current. The FE-HZO FETs is operated at room temperature and 150K to obtain beyond the physical limitation of Boltzmann tyranny, and the extracted body factors are m = 0.67 and m = 0.89 for Vds = 0.1 and 0.5 V, respectively, to confirm the negative capacitance (NC) effect. There are two proposed strategies to reach hysteresis-free, including FE-HZO/epi-Ge/Si FETs with experimentally VT shift 3mV in hysteresis window, and 3nm-thick FE-HZO resulting hysteresis-free and sub-0.2V switching by numerical simulation.

原文	英語
主出版物標題	2015 IEEE International Electron Devices Meeting, IEDM 2015
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	22.5.1-22.5.4
ISBN（電子）	9781467398930
DOIs	https://doi.org/10.1109/IEDM.2015.7409759
出版狀態	已發佈 - 2015 2月 16
事件	61st IEEE International Electron Devices Meeting, IEDM 2015 - Washington, 美国持續時間: 2015 12月 7 → 2015 12月 9

出版系列

名字	Technical Digest - International Electron Devices Meeting, IEDM
卷	2016-February
ISSN（列印）	0163-1918

其他

其他	61st IEEE International Electron Devices Meeting, IEDM 2015
國家/地區	美国
城市	Washington
期間	2015/12/07 → 2015/12/09

ASJC Scopus subject areas

電子、光磁材料
凝聚態物理學
電氣與電子工程
材料化學

存取文件

10.1109/IEDM.2015.7409759

其它文件與鏈接

引用此

Lee, M. H., Chen, P. G., Liu, C., Chu, K. Y., Cheng, C. C., Xie, M. J., Liu, S. N., Lee, J. W., Huang, S. J., Liao, M. H., Tang, M., Li, K. S., & Chen, M. C. (2015). Prospects for ferroelectric HfZrOx FETs with experimentally CET=0.98nm, SS_for=42mV/dec, SS_rev=28mV/dec, switch-off <0.2V, and hysteresis-free strategies. 於 2015 IEEE International Electron Devices Meeting, IEDM 2015 (頁 22.5.1-22.5.4). 文章 7409759 (Technical Digest - International Electron Devices Meeting, IEDM; 卷 2016-February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2015.7409759

Prospects for ferroelectric HfZrOx FETs with experimentally CET=0.98nm, SS_for=42mV/dec, SS_rev=28mV/dec, switch-off <0.2V, and hysteresis-free strategies. / Lee, M. H.; Chen, P. G.; Liu, C. 等.
2015 IEEE International Electron Devices Meeting, IEDM 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 22.5.1-22.5.4 7409759 (Technical Digest - International Electron Devices Meeting, IEDM; 卷 2016-February).

研究成果: 書貢獻/報告類型 › 會議論文篇章

Lee, MH, Chen, PG, Liu, C, Chu, KY, Cheng, CC, Xie, MJ, Liu, SN, Lee, JW, Huang, SJ, Liao, MH, Tang, M, Li, KS & Chen, MC 2015, Prospects for ferroelectric HfZrOx FETs with experimentally CET=0.98nm, SS_for=42mV/dec, SS_rev=28mV/dec, switch-off <0.2V, and hysteresis-free strategies. 於 2015 IEEE International Electron Devices Meeting, IEDM 2015., 7409759, Technical Digest - International Electron Devices Meeting, IEDM, 卷 2016-February, Institute of Electrical and Electronics Engineers Inc., 頁 22.5.1-22.5.4, 61st IEEE International Electron Devices Meeting, IEDM 2015, Washington, 美国, 2015/12/07. https://doi.org/10.1109/IEDM.2015.7409759

Lee MH, Chen PG, Liu C, Chu KY, Cheng CC, Xie MJ 等. Prospects for ferroelectric HfZrOx FETs with experimentally CET=0.98nm, SS_for=42mV/dec, SS_rev=28mV/dec, switch-off <0.2V, and hysteresis-free strategies. 於 2015 IEEE International Electron Devices Meeting, IEDM 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 22.5.1-22.5.4. 7409759. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM.2015.7409759

Lee, M. H. ; Chen, P. G. ; Liu, C. 等. / Prospects for ferroelectric HfZrOx FETs with experimentally CET=0.98nm, SS_for=42mV/dec, SS_rev=28mV/dec, switch-off <0.2V, and hysteresis-free strategies. 2015 IEEE International Electron Devices Meeting, IEDM 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 頁 22.5.1-22.5.4 (Technical Digest - International Electron Devices Meeting, IEDM).

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title = "Prospects for ferroelectric HfZrOx FETs with experimentally CET=0.98nm, SSfor=42mV/dec, SSrev=28mV/dec, switch-off <0.2V, and hysteresis-free strategies",

abstract = "Ferroelectric HfZrOx (FE-HZO) FETs is experimentally demonstrated with 0.98nm CET (capacitance equivalent thickness), small hysteresis window VT (threshold voltage) shift < 0.1V, SSfor = 42mV/dec, SSrev = 28mV/dec, and switch-off < 0.2V. The optimum ALD process leads single monolayer SiOx for IL (interfacial layer) and low gate leakage current. The FE-HZO FETs is operated at room temperature and 150K to obtain beyond the physical limitation of Boltzmann tyranny, and the extracted body factors are m = 0.67 and m = 0.89 for Vds = 0.1 and 0.5 V, respectively, to confirm the negative capacitance (NC) effect. There are two proposed strategies to reach hysteresis-free, including FE-HZO/epi-Ge/Si FETs with experimentally VT shift 3mV in hysteresis window, and 3nm-thick FE-HZO resulting hysteresis-free and sub-0.2V switching by numerical simulation.",

author = "Lee, \{M. H.\} and Chen, \{P. G.\} and C. Liu and Chu, \{K. Y.\} and Cheng, \{C. C.\} and Xie, \{M. J.\} and Liu, \{S. N.\} and Lee, \{J. W.\} and Huang, \{S. J.\} and Liao, \{M. H.\} and M. Tang and Li, \{K. S.\} and Chen, \{M. C.\}",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 61st IEEE International Electron Devices Meeting, IEDM 2015 ; Conference date: 07-12-2015 Through 09-12-2015",

year = "2015",

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AU - Lee, M. H.

AU - Chen, P. G.

AU - Liu, C.

AU - Chu, K. Y.

AU - Cheng, C. C.

AU - Xie, M. J.

AU - Liu, S. N.

AU - Lee, J. W.

AU - Huang, S. J.

AU - Liao, M. H.

AU - Tang, M.

AU - Li, K. S.

AU - Chen, M. C.

PY - 2015/2/16

Y1 - 2015/2/16

N2 - Ferroelectric HfZrOx (FE-HZO) FETs is experimentally demonstrated with 0.98nm CET (capacitance equivalent thickness), small hysteresis window VT (threshold voltage) shift < 0.1V, SSfor = 42mV/dec, SSrev = 28mV/dec, and switch-off < 0.2V. The optimum ALD process leads single monolayer SiOx for IL (interfacial layer) and low gate leakage current. The FE-HZO FETs is operated at room temperature and 150K to obtain beyond the physical limitation of Boltzmann tyranny, and the extracted body factors are m = 0.67 and m = 0.89 for Vds = 0.1 and 0.5 V, respectively, to confirm the negative capacitance (NC) effect. There are two proposed strategies to reach hysteresis-free, including FE-HZO/epi-Ge/Si FETs with experimentally VT shift 3mV in hysteresis window, and 3nm-thick FE-HZO resulting hysteresis-free and sub-0.2V switching by numerical simulation.

AB - Ferroelectric HfZrOx (FE-HZO) FETs is experimentally demonstrated with 0.98nm CET (capacitance equivalent thickness), small hysteresis window VT (threshold voltage) shift < 0.1V, SSfor = 42mV/dec, SSrev = 28mV/dec, and switch-off < 0.2V. The optimum ALD process leads single monolayer SiOx for IL (interfacial layer) and low gate leakage current. The FE-HZO FETs is operated at room temperature and 150K to obtain beyond the physical limitation of Boltzmann tyranny, and the extracted body factors are m = 0.67 and m = 0.89 for Vds = 0.1 and 0.5 V, respectively, to confirm the negative capacitance (NC) effect. There are two proposed strategies to reach hysteresis-free, including FE-HZO/epi-Ge/Si FETs with experimentally VT shift 3mV in hysteresis window, and 3nm-thick FE-HZO resulting hysteresis-free and sub-0.2V switching by numerical simulation.

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