@inproceedings{1e8905ec492041d3ae605910fd63564e,
title = "Prospects for ferroelectric HfZrOx FETs with experimentally CET=0.98nm, SSfor=42mV/dec, SSrev=28mV/dec, switch-off <0.2V, and hysteresis-free strategies",
abstract = "Ferroelectric HfZrOx (FE-HZO) FETs is experimentally demonstrated with 0.98nm CET (capacitance equivalent thickness), small hysteresis window VT (threshold voltage) shift < 0.1V, SSfor = 42mV/dec, SSrev = 28mV/dec, and switch-off < 0.2V. The optimum ALD process leads single monolayer SiOx for IL (interfacial layer) and low gate leakage current. The FE-HZO FETs is operated at room temperature and 150K to obtain beyond the physical limitation of Boltzmann tyranny, and the extracted body factors are m = 0.67 and m = 0.89 for Vds = 0.1 and 0.5 V, respectively, to confirm the negative capacitance (NC) effect. There are two proposed strategies to reach hysteresis-free, including FE-HZO/epi-Ge/Si FETs with experimentally VT shift 3mV in hysteresis window, and 3nm-thick FE-HZO resulting hysteresis-free and sub-0.2V switching by numerical simulation.",
author = "Lee, {M. H.} and Chen, {P. G.} and C. Liu and Chu, {K. Y.} and Cheng, {C. C.} and Xie, {M. J.} and Liu, {S. N.} and Lee, {J. W.} and Huang, {S. J.} and Liao, {M. H.} and M. Tang and Li, {K. S.} and Chen, {M. C.}",
note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 61st IEEE International Electron Devices Meeting, IEDM 2015 ; Conference date: 07-12-2015 Through 09-12-2015",
year = "2015",
month = feb,
day = "16",
doi = "10.1109/IEDM.2015.7409759",
language = "English",
series = "Technical Digest - International Electron Devices Meeting, IEDM",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "22.5.1--22.5.4",
booktitle = "2015 IEEE International Electron Devices Meeting, IEDM 2015",
}