Program/erase speed and data retention trade-off in negative capacitance versatile memory

Chia Chi Fan, Yu Chien Chiu, Chien Liu, Guan Lin Liou, Wen Wei Lai, Yi Ru Chen, Tun Jen Chang, Wan Hsin Chen, Chun Hu Cheng, Chun Yen Chang

研究成果: 書貢獻/報告類型會議論文篇章

摘要

In this work, we investigated the performance tradeoff between program/erase speed and data retention of ferroelectric HfZrO memory. The monoclinic HfNO layer with a trapping mechanism was employed to improve the data retention. Under the thickness optimization of HfNO, the HfZrO/HfNO gate stack can be functionalized with volatile and non-volatile operation.

原文英語
主出版物標題2017 Silicon Nanoelectronics Workshop, SNW 2017
發行者Institute of Electrical and Electronics Engineers Inc.
頁面101-102
頁數2
ISBN(電子)9784863486478
DOIs
出版狀態已發佈 - 2017 十二月 29
事件22nd Silicon Nanoelectronics Workshop, SNW 2017 - Kyoto, 日本
持續時間: 2017 六月 42017 六月 5

出版系列

名字2017 Silicon Nanoelectronics Workshop, SNW 2017
2017-January

其他

其他22nd Silicon Nanoelectronics Workshop, SNW 2017
國家/地區日本
城市Kyoto
期間2017/06/042017/06/05

ASJC Scopus subject areas

  • 電氣與電子工程
  • 電子、光磁材料

指紋

深入研究「Program/erase speed and data retention trade-off in negative capacitance versatile memory」主題。共同形成了獨特的指紋。

引用此