Power-Line-Triggered ESD Protection SCR for 0–20 GHz Applications in CMOS Technology

Chun Rong Chang, Chun Yu Lin*

*此作品的通信作者

研究成果: 雜誌貢獻期刊論文同行評審

摘要

The high-speed circuits fabricated in the CMOS process are sensitive to the electrostatic discharge (ESD), so the ESD protection circuits are required in the chips. The protection circuit should not seriously impact the performance of high-speed circuits and provide wider bandwidth. In this work, a 0–20 GHz ESD protection design using a distributed structure with a novel power-line-triggered silicon-controlled rectifier (PLTSCR) is proposed. This protection circuit is demonstrated in a CMOS process, and the proposed design has been investigated to have area reduction and better ESD protection ability for high-speed applications.

原文英語
頁(從 - 到)6103-6109
頁數7
期刊IEEE Transactions on Electron Devices
70
發行號12
DOIs
出版狀態已發佈 - 2023 12月 1

ASJC Scopus subject areas

  • 電子、光磁材料
  • 電氣與電子工程

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