The fabless integrated circuit (IC) design is one of the most important sectors of the semiconductor industry. In 2010, the total revenue of the fabless IC design sector had already hit US$59.6 billion, accounting for one-fifth of the total semiconductor industry revenue. Thus, understanding the efficiency of fabless IC design houses is critical not only for managers of fabless IC design houses, but semiconductor foundries and investors as well. However, very few researches have tried to benchmark fabless IC design houses. Most existing researches have focused on benchmarking the fabless IC design houses within a particular geographic area, such as Taiwan. Further, very few of the researches that tried to benchmark the world's leading fabless IC design houses introduced the traditional CCR or BCC Data Envelopment Analysis (DEA) models based on improper weight derivations. Such performance evaluation results were derived based on different bases of comparisons of decision-making units (DMUs). Therefore, the purpose of this paper is to evaluate the efficiency of the world's leading fabless IC design houses by introducing a new and reasonable Multiple Objectives Programming (MOP)-based DEA method with derivations of the efficiency achievement measure (EAM). The performance of the world's top forty fabless IC design houses will be evaluated. According to the analytic results, the strength and weakness of IC design houses can be demonstrated and strategies for enhancing the houses can be proposed. In the future, the proposed MOP based DEA method can serve as an appropriate method for performance evaluations.
|頁（從 - 到）||5899-5916|
|期刊||International Journal of Innovative Computing, Information and Control|
|出版狀態||已發佈 - 2012 八月|
ASJC Scopus subject areas