Parallel pipelined histogram architecture via C-slow retiming

Jose O. Cadenas*, R. Simon Sherratt, Pablo Huerta, Wen-Chung Kao, Graham Megson

*此作品的通信作者

研究成果: 書貢獻/報告類型會議論文篇章

1 引文 斯高帕斯(Scopus)

摘要

A parallel pipelined array of cells suitable for realtime computation of histograms is proposed. The cell architecture builds on previous work to now allow operating on a stream of data at 1 pixel per clock cycle. This new cell is more suitable for interfacing to camera sensors or to microprocessors of 8-bit data buses which are common in consumer digital cameras. Arrays using the new proposed cells are obtained via C-slow retiming techniques and can be clocked at a 65% faster frequency than previous arrays. This achieves over 80% of the performance of two-pixel per clock cycle parallel pipelined arrays.

原文英語
主出版物標題2013 IEEE International Conference on Consumer Electronics, ICCE 2013
頁面230-231
頁數2
DOIs
出版狀態已發佈 - 2013 四月 24
事件2013 IEEE International Conference on Consumer Electronics, ICCE 2013 - Las Vegas, NV, 美国
持續時間: 2013 一月 112013 一月 14

出版系列

名字Digest of Technical Papers - IEEE International Conference on Consumer Electronics
ISSN(列印)0747-668X

其他

其他2013 IEEE International Conference on Consumer Electronics, ICCE 2013
國家/地區美国
城市Las Vegas, NV
期間2013/01/112013/01/14

ASJC Scopus subject areas

  • 工業與製造工程
  • 電氣與電子工程

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