Parallel pipelined array architectures for real-time histogram computation in consumer devices

José O. Cadenas, R. Simon Sherratt, Pablo Huerta, Wen Chung Kao

研究成果: 雜誌貢獻文章同行評審

9 引文 斯高帕斯(Scopus)

摘要

The real-time parallel computation of histograms using an array of pipelined cells is proposed and prototyped in this paper with application to consumer imaging products. The array operates in two modes: histogram computation and histogram reading. The proposed parallel computation method does not use any memory blocks. The resulting histogram bins can be stored into an external memory block in a pipelined fashion for subsequent reading or streaming of the results. The array of cells can be tuned to accommodate the required data path width in a VLSI image processing engine as present in many imaging consumer devices. Synthesis of the architectures presented in this paper in FPGA are shown to compute the real-time histogram of images streamed at over 36 megapixels at 30 frames/s by processing in parallel 1, 2 or 4 pixels per clock cycle 1.

原文英語
文章編號6131111
頁(從 - 到)1460-1464
頁數5
期刊IEEE Transactions on Consumer Electronics
57
發行號4
DOIs
出版狀態已發佈 - 2011 十一月 1

ASJC Scopus subject areas

  • Media Technology
  • Electrical and Electronic Engineering

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