Overview on ESD protection designs of low-parasitic capacitance for RF ICs in CMOS technologies

Ming Dou Ker, Chun Yu Lin, Yuan Wen Hsiao

研究成果: 雜誌貢獻综述文章

44 引文 斯高帕斯(Scopus)

摘要

CMOS technology has been widely used to implement radio-frequency integrated circuits (RF ICs). However, the thinner gate oxide in nanoscale CMOS technology seriously degrades the electrostatic discharge (ESD) robustness of RF ICs. Therefore, on-chip ESD protection designs must be added at all input/output pads in RF circuits against ESD damages. To minimize the impacts from ESD protection circuit on RF performances, ESD protection circuit at input/output pads must be carefully designed. An overview on ESD protection designs with low parasitic capacitance for RF circuits in CMOS technology is presented in this paper. The comparisons among these ESD protection designs are also discussed. With the reduced parasitic capacitance, ESD protection circuit can be easily combined or co-designed with RF circuits. As the operating frequencies of RF circuits increase, on-chip ESD protection designs for RF applications will continuously be an important design task.

原文英語
文章編號5688227
頁(從 - 到)207-218
頁數12
期刊IEEE Transactions on Device and Materials Reliability
11
發行號2
DOIs
出版狀態已發佈 - 2011 六月

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Safety, Risk, Reliability and Quality
  • Electrical and Electronic Engineering

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