TY - GEN
T1 - Optimization on SCR device with low capacitance for on-chip ESD protection in UWB RF circuits
AU - Lin, Chun Yu
AU - Ker, Ming Dou
PY - 2008
Y1 - 2008
N2 - Low capacitance (low-C) design on ESD protection device is a solution to mitigate the radio-frequency (RF) performance degradation caused by electrostatic discharge (ESD) protection device. Silicon-controlled rectifier (SCR) device has been used as an effective on-chip ESD protection device in RF ICs due to the smaller layout area and small parasitic capacitance under the same ESD robustness. In this paper, the modified lateral SCR (MLSCR) realized in waffle layout structure is studied to minimize the parasitic capacitance and the variation of the parasitic capacitance within ultra-wide band (UWB) frequencies. With the minimized parasitic capacitance, the degradation on RF circuit performance due to ESD protection devices can be reduced. The waffle MLSCR with low parasitic capacitance is suitable for on-chip ESD protection in UWB RF ICs. Besides, the turn-on speed of MLSCR with waffle layout structure is verified to be better than that with conventional stripe structure.
AB - Low capacitance (low-C) design on ESD protection device is a solution to mitigate the radio-frequency (RF) performance degradation caused by electrostatic discharge (ESD) protection device. Silicon-controlled rectifier (SCR) device has been used as an effective on-chip ESD protection device in RF ICs due to the smaller layout area and small parasitic capacitance under the same ESD robustness. In this paper, the modified lateral SCR (MLSCR) realized in waffle layout structure is studied to minimize the parasitic capacitance and the variation of the parasitic capacitance within ultra-wide band (UWB) frequencies. With the minimized parasitic capacitance, the degradation on RF circuit performance due to ESD protection devices can be reduced. The waffle MLSCR with low parasitic capacitance is suitable for on-chip ESD protection in UWB RF ICs. Besides, the turn-on speed of MLSCR with waffle layout structure is verified to be better than that with conventional stripe structure.
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U2 - 10.1109/IPFA.2008.4588154
DO - 10.1109/IPFA.2008.4588154
M3 - Conference contribution
AN - SCOPUS:51949109264
SN - 1424420393
SN - 9781424420391
T3 - Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
BT - 2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
T2 - 2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
Y2 - 7 July 2008 through 11 July 2008
ER -