Optimization on layout style of diode stackup for on-chip ESD protection

Chun Yu Lin; Mei Lian Fan

doi:10.1109/TDMR.2014.2311130

Optimization on layout style of diode stackup for on-chip ESD protection

Chun Yu Lin, Mei Lian Fan

電機工程學系

研究成果: 雜誌貢獻 › 期刊論文 › 同行評審

7 引文斯高帕斯（Scopus）

摘要

The diode stackup has been used as on-chip electrostatic discharge (ESD) protection for some applications in which the input/output signal swing is higher than V_DD or lower than V_SS. A novel ESD protection structure of diode stackup is proposed for effective on-chip ESD protection. Experimental results in 65-nm CMOS process show that the optimization on layout style can improve the ESD robustness, decrease the turn-on resistance, and lessen the parasitic capacitance of the diode stackup.

原文	英語
文章編號	6763105
頁（從 - 到）	775-777
頁數	3
期刊	IEEE Transactions on Device and Materials Reliability
卷	14
發行號	2
DOIs	https://doi.org/10.1109/TDMR.2014.2311130
出版狀態	已發佈 - 2014 6月

ASJC Scopus subject areas

電子、光磁材料
安全、風險、可靠性和品質
電氣與電子工程

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10.1109/TDMR.2014.2311130

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@article{1c50e381cf184aae8ded60ebd6e6a3c4,

title = "Optimization on layout style of diode stackup for on-chip ESD protection",

abstract = "The diode stackup has been used as on-chip electrostatic discharge (ESD) protection for some applications in which the input/output signal swing is higher than VDD or lower than VSS. A novel ESD protection structure of diode stackup is proposed for effective on-chip ESD protection. Experimental results in 65-nm CMOS process show that the optimization on layout style can improve the ESD robustness, decrease the turn-on resistance, and lessen the parasitic capacitance of the diode stackup.",

keywords = "Diode, electrostatic discharge (ESD), layout, stackup",

author = "Lin, {Chun Yu} and Fan, {Mei Lian}",

year = "2014",

month = jun,

doi = "10.1109/TDMR.2014.2311130",

language = "English",

volume = "14",

pages = "775--777",

journal = "IEEE Transactions on Device and Materials Reliability",

issn = "1530-4388",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "2",

}

TY - JOUR

T1 - Optimization on layout style of diode stackup for on-chip ESD protection

AU - Lin, Chun Yu

AU - Fan, Mei Lian

PY - 2014/6

Y1 - 2014/6

N2 - The diode stackup has been used as on-chip electrostatic discharge (ESD) protection for some applications in which the input/output signal swing is higher than VDD or lower than VSS. A novel ESD protection structure of diode stackup is proposed for effective on-chip ESD protection. Experimental results in 65-nm CMOS process show that the optimization on layout style can improve the ESD robustness, decrease the turn-on resistance, and lessen the parasitic capacitance of the diode stackup.

AB - The diode stackup has been used as on-chip electrostatic discharge (ESD) protection for some applications in which the input/output signal swing is higher than VDD or lower than VSS. A novel ESD protection structure of diode stackup is proposed for effective on-chip ESD protection. Experimental results in 65-nm CMOS process show that the optimization on layout style can improve the ESD robustness, decrease the turn-on resistance, and lessen the parasitic capacitance of the diode stackup.

KW - Diode

KW - electrostatic discharge (ESD)

KW - layout

KW - stackup

UR - http://www.scopus.com/inward/record.url?scp=84902141438&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84902141438&partnerID=8YFLogxK

U2 - 10.1109/TDMR.2014.2311130

DO - 10.1109/TDMR.2014.2311130

M3 - Article

AN - SCOPUS:84902141438

SN - 1530-4388

VL - 14

SP - 775

EP - 777

JO - IEEE Transactions on Device and Materials Reliability

JF - IEEE Transactions on Device and Materials Reliability

IS - 2

M1 - 6763105

ER -

Optimization on layout style of diode stackup for on-chip ESD protection

摘要

ASJC Scopus subject areas

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