Optimization on layout style of diode stackup for on-chip ESD protection

Chun Yu Lin, Mei Lian Fan

研究成果: 雜誌貢獻期刊論文同行評審

7 引文 斯高帕斯(Scopus)

摘要

The diode stackup has been used as on-chip electrostatic discharge (ESD) protection for some applications in which the input/output signal swing is higher than VDD or lower than VSS. A novel ESD protection structure of diode stackup is proposed for effective on-chip ESD protection. Experimental results in 65-nm CMOS process show that the optimization on layout style can improve the ESD robustness, decrease the turn-on resistance, and lessen the parasitic capacitance of the diode stackup.

原文英語
文章編號6763105
頁(從 - 到)775-777
頁數3
期刊IEEE Transactions on Device and Materials Reliability
14
發行號2
DOIs
出版狀態已發佈 - 2014 六月

ASJC Scopus subject areas

  • 電子、光磁材料
  • 安全、風險、可靠性和品質
  • 電氣與電子工程

指紋

深入研究「Optimization on layout style of diode stackup for on-chip ESD protection」主題。共同形成了獨特的指紋。

引用此