Optimization of regular expression pattern matching circuits on FPGA

Cheng-Hung Lin, Chih Tsun Huang, Chang Ping Jiang, Shih Chieh Chang

研究成果: 書貢獻/報告類型會議貢獻

50 引文 斯高帕斯(Scopus)

摘要

Regular expressions are widely used in Network Intrusion Detection System (NIDS) to represent patterns of network attacks. Since traditional software-only NIDS cannot catch up to the speed advance of networks, many previous works propose hardware architectures on FPGA to accelerate attack detection. The challenge of hardware implementation is to accommodate the regular expressions to FPGAs of the large number of attacks. Although the minimization of logic equations has been studied intensively in the CAD area, the minimization of multiple regular expressions has been largely neglected. This paper presents a novel architecture allowing our algorithm to extract and share common sub-regular expressions. Experimental results show that our sharing scheme significantly reduces the area of regular expression circuits.

原文英語
主出版物標題Proceedings - Design, Automation and Test in Europe, DATE'06
DOIs
出版狀態已發佈 - 2006 十二月 1
事件Design, Automation and Test in Europe, DATE'06 - Munich, 德国
持續時間: 2006 三月 62006 三月 10

出版系列

名字Proceedings -Design, Automation and Test in Europe, DATE
2
ISSN(列印)1530-1591

其他

其他Design, Automation and Test in Europe, DATE'06
國家德国
城市Munich
期間06/3/606/3/10

    指紋

ASJC Scopus subject areas

  • Engineering(all)

引用此

Lin, C-H., Huang, C. T., Jiang, C. P., & Chang, S. C. (2006). Optimization of regular expression pattern matching circuits on FPGA. 於 Proceedings - Design, Automation and Test in Europe, DATE'06 [1657107] (Proceedings -Design, Automation and Test in Europe, DATE; 卷 2). https://doi.org/10.1109/DATE.2004.1269064