Optimization of pattern matching circuits for regular expression on FPGA

Cheng Hung Lin*, Chih Tsun Huang, Chang Ping Jiang, Shih Chieh Chang

*此作品的通信作者

研究成果: 雜誌貢獻期刊論文同行評審

42 引文 斯高帕斯(Scopus)

摘要

Regular expressions are widely used in the network intrusion detection system (NIDS) to represent attack patterns. Previously, many hardware architectures have been proposed to accelerate regular expression matching using field-programmable gate array (FPGA) because FPGAs allow updating of new attack patterns. Because of the increasing number of attacks, we need to accommodate a large number of regular expressions on FPGAs. Although the minimization of logic equations has been studied intensively in the area of computer-aided design (CAD), the minimization of multiple regular expressions has been largely neglected. This paper presents a novel sharing architecture allowing our algorithm to extract and share common subregular expressions. Experimental results show that our sharing scheme significantly reduces the area of pattern matching circuits for regular expression.

原文英語
頁(從 - 到)1303-1310
頁數8
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
15
發行號12
DOIs
出版狀態已發佈 - 2007 十二月

ASJC Scopus subject areas

  • 軟體
  • 硬體和架構
  • 電氣與電子工程

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