On-Chip HBM and HMM ESD Protection Design for RF Applications in 40-nm CMOS Process

Jie Ting Chen, Chun Yu Lin, Rong Kun Chang, Ming Dou Ker

研究成果: 雜誌貢獻文章

摘要

On-chip electrostatic discharge (ESD) protection device with large dimension can sustain high-ESD current, but the parasitic capacitance of the ESD protection device will increase the difficulty of impedance matching and degrade the bandwidth for broadband radio frequency (RF) applications. The traditional distributed ESD protection circuit can achieve good impedance matching, but it has a worse ESD robustness because of larger resistance caused by the input inductor. In this paper, a new distributed ESD protection structure with the stacked diodes with embedded silicon-controlled rectifier is proposed to attain good ESD robustness without degrading the RF performance. The proposed ESD protection circuit has been successfully verified in a 40-nm, 2.5-V CMOS process to sustain a human-metal model of 5 kV. The proposed ESD protection circuit is suitable to protect the broadband RF circuits in advanced nanoscale CMOS technology.

原文英語
文章編號8501596
頁(從 - 到)5267-5274
頁數8
期刊IEEE Transactions on Electron Devices
65
發行號12
DOIs
出版狀態已發佈 - 2018 十二月 1

指紋

Electrostatic discharge
Networks (circuits)
Thyristors
Diodes
Capacitance
Metals
Bandwidth

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

引用此文

On-Chip HBM and HMM ESD Protection Design for RF Applications in 40-nm CMOS Process. / Chen, Jie Ting; Lin, Chun Yu; Chang, Rong Kun; Ker, Ming Dou.

於: IEEE Transactions on Electron Devices, 卷 65, 編號 12, 8501596, 01.12.2018, p. 5267-5274.

研究成果: 雜誌貢獻文章

Chen, Jie Ting ; Lin, Chun Yu ; Chang, Rong Kun ; Ker, Ming Dou. / On-Chip HBM and HMM ESD Protection Design for RF Applications in 40-nm CMOS Process. 於: IEEE Transactions on Electron Devices. 2018 ; 卷 65, 編號 12. 頁 5267-5274.
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