TY - GEN
T1 - Negative Capacitance CMOS Field-Effect Transistors with Non-Hysteretic Steep Sub-60mV/dec Swing and Defect-Passivated Multidomain Switching
AU - Liu, Chien
AU - Chen, Hsuan Han
AU - Hsu, Chih Chieh
AU - Fan, Chia Chi
AU - Hsu, Hsiao Hsuan
AU - Cheng, Chun Hu
N1 - Publisher Copyright:
© 2019 The Japan Society of Applied Physics.
PY - 2019/6
Y1 - 2019/6
N2 - We demonstrated that the 2.5nm-thick HfAIOx N-type NCFET based on defect-passivated multidomain switching can achieve a minimum 9 mV/dec subthreshold swing (SS), a negligible hysteresis of 1mV, an ultralow Ioff of 135fA/μm, a large Ion/I0ff ratio of 8.7×107 and a sub-60 mV/dec SS over 5 decade. For P-type NCFET, the non-hysteretic steep-slope switch is still reached under the synergistic effect of gate stress, defect passivation and doping engineering. The Al doping and defect passivation play the key role for reducing trap-related leakage, enhancing NC, and stabilizing multidomain switching. The highly scaled HfAIOx CMOS NCFET shows the potential for low power logic applications.
AB - We demonstrated that the 2.5nm-thick HfAIOx N-type NCFET based on defect-passivated multidomain switching can achieve a minimum 9 mV/dec subthreshold swing (SS), a negligible hysteresis of 1mV, an ultralow Ioff of 135fA/μm, a large Ion/I0ff ratio of 8.7×107 and a sub-60 mV/dec SS over 5 decade. For P-type NCFET, the non-hysteretic steep-slope switch is still reached under the synergistic effect of gate stress, defect passivation and doping engineering. The Al doping and defect passivation play the key role for reducing trap-related leakage, enhancing NC, and stabilizing multidomain switching. The highly scaled HfAIOx CMOS NCFET shows the potential for low power logic applications.
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U2 - 10.23919/VLSIT.2019.8776482
DO - 10.23919/VLSIT.2019.8776482
M3 - Conference contribution
AN - SCOPUS:85070319546
T3 - Digest of Technical Papers - Symposium on VLSI Technology
SP - T224-T225
BT - 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 39th Symposium on VLSI Technology, VLSI Technology 2019
Y2 - 9 June 2019 through 14 June 2019
ER -