Negative bias temperature instability (NBTI) in deep sub-micron p+-gate pMOSFETs

Y. F. Chen*, M. H. Lin, C. H. Chou, W. C. Chang, S. C. Huang, Y. J. Chang, K. Y. Fu, M. T. Lee, C. H. Liu, S. K. Fan

*此作品的通信作者

研究成果: 會議貢獻類型會議論文同行評審

20 引文 斯高帕斯(Scopus)

摘要

The device degradation, characterized by threshold voltage shift (ΔVth), in deep sub-micron p+ polysilicon gate pMOSFETs due to negative bias temperature instability (NBTI) stress is studied. It is found that the negative threshold voltage shift tends to saturate with stress time. Both hydrogen ions and neutral atoms are believed to contribute to the generation of interface states. The I-V characteristics are compared before and after stresses and it shows that the interface degradation is symmetrical for S/D. In this work, a simple physical model is proposed to qualitatively explain the time evolution of the negative threshold voltage shift ΔVth. This saturation implies continued formation of oxide-trapped holes and the accumulation of positive fixed oxide charges, inhibiting further transport of hydrogen ions and resulting in a gradual decrease in interface trap formation. Moreover, the activation energy EA and field-acceleration parameter are also extracted to establish a general phenomenological model to predict the device lifetime of pMOSFETs characterized by threshold voltage shift.

原文英語
頁面98-101
頁數4
出版狀態已發佈 - 2000
事件2000 IEEE International Integrated Reliability Workshop - Lake Tahoe, CA, USA
持續時間: 2000 十月 232000 十月 26

其他

其他2000 IEEE International Integrated Reliability Workshop
城市Lake Tahoe, CA, USA
期間2000/10/232000/10/26

ASJC Scopus subject areas

  • 電氣與電子工程
  • 工業與製造工程

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