NBTI mechanism explored on the back gate bias for pMOSFETs

M. G. Chen, J. S. Li, C. Jiang, C. H. Liu, K. C. Su, Y. H. Chang

研究成果: 書貢獻/報告類型會議論文篇章

5 引文 斯高帕斯(Scopus)

摘要

Negative bias temperature instability had been getting more attention with the scaling down of MOS transistor, accompanied by the thinning of gate oxide. In our experiment of 0.15μm dual gate CMOS process, it is shown that surface hole concentration will have much impact on NBTI by means of Vsb application, no matter for devices of 2.6-nm or 6.5-nm oxide thickness. The NBTI enhancement at high Vsb is believed to be caused by the substrate hot hole injection, which leads to more interface state and positive charge generation, and thus makes NBTI worse. On the other hand, we expect better NBTI results under low gate electric field with Vsb applied, due to reduction of surface hole from Vsb.

原文英語
主出版物標題2003 IEEE International Integrated Reliability Workshop Final Report, IRW 2003
發行者Institute of Electrical and Electronics Engineers Inc.
頁面131-132
頁數2
ISBN(電子)0780381572
DOIs
出版狀態已發佈 - 2003
對外發佈
事件2003 IEEE International Integrated Reliability Workshop, IRW 2003 - Lake Tahoe, 美国
持續時間: 2003 10月 202003 10月 23

出版系列

名字IEEE International Integrated Reliability Workshop Final Report
2003-January

會議

會議2003 IEEE International Integrated Reliability Workshop, IRW 2003
國家/地區美国
城市Lake Tahoe
期間2003/10/202003/10/23

ASJC Scopus subject areas

  • 電氣與電子工程
  • 安全、風險、可靠性和品質
  • 電子、光磁材料

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