TY - JOUR
T1 - Multi-bit delta-sigma modulator using a modified DWA algorithm
AU - Kuo, Chien Hung
AU - Hsueh, Tzu Chien
AU - Liu, Shen Iuan
PY - 2002/12
Y1 - 2002/12
N2 - A four pointer data weighted averaging (FPDWA) algorithm is presented to reduce the nonlinearity of the feedback multi-bit digital-to-analog converter (DAC) for delta-sigma modulators. By utilizing the proposed algorithm, the noise power caused by element mismatch can be reduced. A nine-level second-order delta-sigma modulator has been implemented in a double-poly double-metal 0.35 μm CMOS process. Experimental results indicate the peak SNDR reaches 86.59 dB within bandwidth of 22 kHz. The maximum input amplitude is -7 dB below the full scale with 10-kHz input frequency, the sampling frequency is 5 MHz, and the OSR is around 113. The power consumption is 6.27 mW for a power supply of 3.3 V.
AB - A four pointer data weighted averaging (FPDWA) algorithm is presented to reduce the nonlinearity of the feedback multi-bit digital-to-analog converter (DAC) for delta-sigma modulators. By utilizing the proposed algorithm, the noise power caused by element mismatch can be reduced. A nine-level second-order delta-sigma modulator has been implemented in a double-poly double-metal 0.35 μm CMOS process. Experimental results indicate the peak SNDR reaches 86.59 dB within bandwidth of 22 kHz. The maximum input amplitude is -7 dB below the full scale with 10-kHz input frequency, the sampling frequency is 5 MHz, and the OSR is around 113. The power consumption is 6.27 mW for a power supply of 3.3 V.
UR - http://www.scopus.com/inward/record.url?scp=0036891793&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0036891793&partnerID=8YFLogxK
U2 - 10.1023/A:1020769913779
DO - 10.1023/A:1020769913779
M3 - Article
AN - SCOPUS:0036891793
SN - 0925-1030
VL - 33
SP - 289
EP - 300
JO - Analog Integrated Circuits and Signal Processing
JF - Analog Integrated Circuits and Signal Processing
IS - 3
ER -