Multi-bit delta-sigma modulator using a modified DWA algorithm

Chien Hung Kuo, Tzu Chien Hsueh, Shen Iuan Liu

研究成果: 雜誌貢獻文章

摘要

A four pointer data weighted averaging (FPDWA) algorithm is presented to reduce the nonlinearity of the feedback multi-bit digital-to-analog converter (DAC) for delta-sigma modulators. By utilizing the proposed algorithm, the noise power caused by element mismatch can be reduced. A nine-level second-order delta-sigma modulator has been implemented in a double-poly double-metal 0.35 μm CMOS process. Experimental results indicate the peak SNDR reaches 86.59 dB within bandwidth of 22 kHz. The maximum input amplitude is -7 dB below the full scale with 10-kHz input frequency, the sampling frequency is 5 MHz, and the OSR is around 113. The power consumption is 6.27 mW for a power supply of 3.3 V.

原文英語
頁(從 - 到)289-300
頁數12
期刊Analog Integrated Circuits and Signal Processing
33
發行號3
DOIs
出版狀態已發佈 - 2002 十二月

    指紋

ASJC Scopus subject areas

  • Signal Processing
  • Hardware and Architecture
  • Surfaces, Coatings and Films

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