TY - GEN
T1 - Modeling and Optimization of the Channel-All-Around (CAA) FeFETs
AU - Li, Pei Ying
AU - Liao, Hsin Tzu
AU - Lee, Jia Yang
AU - Lee, Min Hung
N1 - Publisher Copyright:
© 2026 IEEE.
PY - 2026
Y1 - 2026
N2 - This work discussed the electrical characteristics of GAA and CAA FeFETs based on 3D TCAD simulation. Compared with GAA FeFETs, CAA FeFETs exhibit higher Ion, 3.6x larger MW, and more negative VT. To optimize the CAA structure design, the layer thickness and CD variation are taken into consideration. It reveals that the voltage division across different layers is a key factor in both MW and SS, and the optimized CAA FeFET design demonstrates a maximum MW of 1.128 V.
AB - This work discussed the electrical characteristics of GAA and CAA FeFETs based on 3D TCAD simulation. Compared with GAA FeFETs, CAA FeFETs exhibit higher Ion, 3.6x larger MW, and more negative VT. To optimize the CAA structure design, the layer thickness and CD variation are taken into consideration. It reveals that the voltage division across different layers is a key factor in both MW and SS, and the optimized CAA FeFET design demonstrates a maximum MW of 1.128 V.
KW - Channel-All-Around (CAA)
KW - ferroelectric field effect transistor (FeFET)
KW - Gate-All-Around (GAA)
UR - https://www.scopus.com/pages/publications/105041870290
UR - https://www.scopus.com/pages/publications/105041870290#tab=citedBy
U2 - 10.1109/VLSITSA69131.2026.11527494
DO - 10.1109/VLSITSA69131.2026.11527494
M3 - Conference contribution
AN - SCOPUS:105041870290
T3 - 2026 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2026 - Proceedings of Technical Papers
BT - 2026 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2026 - Proceedings of Technical Papers
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2026 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2026
Y2 - 13 April 2026 through 17 April 2026
ER -