Metal-gate/high-κ CMOS scaling from Si to Ge at small EOT

Albert Chin, W. B. Chen, B. S. Shie, K. C. Hsu, P. C. Chen, C. H. Cheng, C. C. Chi, Y. H. Wu, K. S. Chaing-Liaoc, S. J. Wang, C. H. Kuan, F. S. Yeh

研究成果: 書貢獻/報告類型會議論文篇章

2 引文 斯高帕斯(Scopus)

摘要

Continuously down-scaling EOT and improving mobility are required for CMOS device. Small 0.6∼1 nm EOT and low Vt of ∼0.15 V are achieved in CMOS by using higher κ gate dielectric and novel process. The ultimate EOT scaling is limited by the inserted ultra-thin SiON interfacial layer in high-κ/Si to reduce the mobility degradation. Further mobility improvement is obtained by using Ge channel MOSFET that has 2.5X better high-field hole effective mobility than the SiO2/Si universal mobility at an E eff of 1 MV/cm.

原文英語
主出版物標題ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings
頁面836-839
頁數4
DOIs
出版狀態已發佈 - 2010
事件2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology - Shanghai, 中国
持續時間: 2010 十一月 12010 十一月 4

出版系列

名字ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings

其他

其他2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology
國家/地區中国
城市Shanghai
期間2010/11/012010/11/04

ASJC Scopus subject areas

  • 硬體和架構
  • 電氣與電子工程

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