Memory-efficient pattern matching architectures using perfect hashing on graphic processing units

Cheng Hung Lin*, Chen Hsiung Liu, Shih Chieh Chang, Wing Kai Hon

*此作品的通信作者

研究成果: 書貢獻/報告類型會議論文篇章

12 引文 斯高帕斯(Scopus)

摘要

Memory architectures have been widely adopted in network intrusion detection system for inspecting malicious packets due to their flexibility and scalability. Memory architectures match input streams against thousands of attack patterns by traversing the corresponding state transition table stored in commodity memories. With the increasing number of attack patterns, reducing memory requirement has become critical for memory architectures. In this paper, we propose a novel memory architecture using perfect hashing to condense state transition tables without hash collisions. The proposed memory architecture achieves up to 99.5% improvement in memory reduction compared to the traditional two-dimensional memory architecture. We have implemented our memory architectures on graphic processing units and tested using attack patterns from Snort V2.8 and input packets form DEFCON. The experimental results show that the proposed memory architectures outperform state-of-the-art memory architectures both on performance and memory efficiency.

原文英語
主出版物標題2012 Proceedings IEEE INFOCOM, INFOCOM 2012
頁面1978-1986
頁數9
DOIs
出版狀態已發佈 - 2012
事件IEEE Conference on Computer Communications, INFOCOM 2012 - Orlando, FL, 美国
持續時間: 2012 三月 252012 三月 30

出版系列

名字Proceedings - IEEE INFOCOM
ISSN(列印)0743-166X

其他

其他IEEE Conference on Computer Communications, INFOCOM 2012
國家/地區美国
城市Orlando, FL
期間2012/03/252012/03/30

ASJC Scopus subject areas

  • 電腦科學(全部)
  • 電氣與電子工程

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