摘要
The physical mechanism responsible for negative bias temperature instability (NBTI), which is basic to the minimization of this degradation mode, is investigated, and an analytical model is developed accordingly. Experiments with 1.7 nm to 3.3 nm gate dielectrics fabricated by different processes demonstrate the capability of the proposed model.
| 原文 | 英語 |
|---|---|
| 頁(從 - 到) | 2423-2425 |
| 頁數 | 3 |
| 期刊 | Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers |
| 卷 | 41 |
| 發行號 | 4 B |
| DOIs | |
| 出版狀態 | 已發佈 - 2002 4月 |
| 對外發佈 | 是 |
ASJC Scopus subject areas
- 一般工程
- 一般物理與天文學
指紋
深入研究「Mechanism of threshold voltage shift (Δ Vth) caused by negative bias temperature instability (NBTI) in deep submicron pMOSFETs」主題。共同形成了獨特的指紋。引用此
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