Low-threshold-voltage TaN/Ir/LaTiO p-MOSFETs incorporating low-temperature-formed shallow junctions

S. H. Lin; C. H. Cheng; W. B. Chen; F. S. Yeh; Albert Chin

doi:10.1109/LED.2009.2020307

Low-threshold-voltage TaN/Ir/LaTiO p-MOSFETs incorporating low-temperature-formed shallow junctions

S. H. Lin^*
, C. H. Cheng
, W. B. Chen
, F. S. Yeh
, Albert Chin

^*此作品的通信作者

研究成果: 雜誌貢獻 › 期刊論文 › 同行評審

5 引文斯高帕斯（Scopus）

摘要

We demonstrate a low threshold voltage (V_t) of -0.17 V and good hole mobility (54 cm²/V · s at 0.8 MV/cm) in TaN/ Ir/LaTiO p-MOSFETs at an equivalent oxide thickness of only 0.66 nm. This was achieved by using Ni-induced solid-phase diffusion of SiO₂-covered Ni/Ga which reduced the high-κ dielectric interfacial reactions. This approach, along with its self-aligned and gate-first process, is compatible with current VLSI technology.

原文	英語
頁（從 - 到）	681-863
頁數	183
期刊	IEEE Electron Device Letters
卷	30
發行號	6
DOIs	https://doi.org/10.1109/LED.2009.2020307
出版狀態	已發佈 - 2009
對外發佈	是

ASJC Scopus subject areas

電子、光磁材料
電氣與電子工程

存取文件

10.1109/LED.2009.2020307

其它文件與鏈接

引用此

@article{281724a63a51461b8d77cf072b7e45bd,

title = "Low-threshold-voltage TaN/Ir/LaTiO p-MOSFETs incorporating low-temperature-formed shallow junctions",

abstract = "We demonstrate a low threshold voltage (Vt) of -0.17 V and good hole mobility (54 cm2/V · s at 0.8 MV/cm) in TaN/ Ir/LaTiO p-MOSFETs at an equivalent oxide thickness of only 0.66 nm. This was achieved by using Ni-induced solid-phase diffusion of SiO2-covered Ni/Ga which reduced the high-κ dielectric interfacial reactions. This approach, along with its self-aligned and gate-first process, is compatible with current VLSI technology.",

keywords = "LaTiO, Low V, Solid-phase diffusion (SPD)",

author = "Lin, \{S. H.\} and Cheng, \{C. H.\} and Chen, \{W. B.\} and Yeh, \{F. S.\} and Albert Chin",

note = "Funding Information: Manuscript received August 8, 2008. First published May 12, 2009; current version published May 27, 2009. This work was supported in part by the National Science Council of Taiwan (NSC 97-2120-M-009-008). The review of this letter was arranged by Editor C. Bulucea.",

year = "2009",

doi = "10.1109/LED.2009.2020307",

language = "English",

volume = "30",

pages = "681--863",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "6",

}

TY - JOUR

T1 - Low-threshold-voltage TaN/Ir/LaTiO p-MOSFETs incorporating low-temperature-formed shallow junctions

AU - Lin, S. H.

AU - Cheng, C. H.

AU - Chen, W. B.

AU - Yeh, F. S.

AU - Chin, Albert

N1 - Funding Information: Manuscript received August 8, 2008. First published May 12, 2009; current version published May 27, 2009. This work was supported in part by the National Science Council of Taiwan (NSC 97-2120-M-009-008). The review of this letter was arranged by Editor C. Bulucea.

PY - 2009

Y1 - 2009

N2 - We demonstrate a low threshold voltage (Vt) of -0.17 V and good hole mobility (54 cm2/V · s at 0.8 MV/cm) in TaN/ Ir/LaTiO p-MOSFETs at an equivalent oxide thickness of only 0.66 nm. This was achieved by using Ni-induced solid-phase diffusion of SiO2-covered Ni/Ga which reduced the high-κ dielectric interfacial reactions. This approach, along with its self-aligned and gate-first process, is compatible with current VLSI technology.

AB - We demonstrate a low threshold voltage (Vt) of -0.17 V and good hole mobility (54 cm2/V · s at 0.8 MV/cm) in TaN/ Ir/LaTiO p-MOSFETs at an equivalent oxide thickness of only 0.66 nm. This was achieved by using Ni-induced solid-phase diffusion of SiO2-covered Ni/Ga which reduced the high-κ dielectric interfacial reactions. This approach, along with its self-aligned and gate-first process, is compatible with current VLSI technology.

KW - LaTiO

KW - Low V

KW - Solid-phase diffusion (SPD)

UR - https://www.scopus.com/pages/publications/67649385958

UR - https://www.scopus.com/pages/publications/67649385958#tab=citedBy

U2 - 10.1109/LED.2009.2020307

DO - 10.1109/LED.2009.2020307

M3 - Article

AN - SCOPUS:67649385958

SN - 0741-3106

VL - 30

SP - 681

EP - 863

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 6

ER -

Low-threshold-voltage TaN/Ir/LaTiO p-MOSFETs incorporating low-temperature-formed shallow junctions

摘要

ASJC Scopus subject areas

存取文件

其它文件與鏈接

指紋

引用此