Low-threshold-voltage TaN/Ir/LaTiO p-MOSFETs incorporating low-temperature-formed shallow junctions

S. H. Lin*, C. H. Cheng, W. B. Chen, F. S. Yeh, Albert Chin

*此作品的通信作者

研究成果: 雜誌貢獻期刊論文同行評審

4 引文 斯高帕斯(Scopus)

摘要

We demonstrate a low threshold voltage (Vt) of -0.17 V and good hole mobility (54 cm2/V · s at 0.8 MV/cm) in TaN/ Ir/LaTiO p-MOSFETs at an equivalent oxide thickness of only 0.66 nm. This was achieved by using Ni-induced solid-phase diffusion of SiO2-covered Ni/Ga which reduced the high-κ dielectric interfacial reactions. This approach, along with its self-aligned and gate-first process, is compatible with current VLSI technology.

原文英語
頁(從 - 到)681-863
頁數183
期刊IEEE Electron Device Letters
30
發行號6
DOIs
出版狀態已發佈 - 2009

ASJC Scopus subject areas

  • 電子、光磁材料
  • 電氣與電子工程

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