Low power 1T DRAM/NVM versatile memory featuring steep sub-60-mV/decade operation, fast 20-ns speed, and robust 85°C-extrapolated 1016 endurance

Yu Chien Chiu, Chun Hu Cheng, Chun Yen Chang, Min Hung Lee, Hsiao Hsuan Hsu, Shiang Shiou Yen

研究成果: 書貢獻/報告類型會議論文篇章

46 引文 斯高帕斯(Scopus)

摘要

In this work, we report a one-transistor (1T) versatile memory; the memory transistor characteristics achieve sub-60-mV/dec operation and considerably low off-state leakage of 10-15 A/μm at a supply voltage below 0.5V. The versatile memory features DRAM/NVM functions of large ΔVT window of 2.8V, fast 20-ns speed, 103s retention at 85°C, and long extrapolated 1016 endurance at 85°C, which show the potential for 3D memory application with severe requirement on both high density and low power consumption.

原文英語
主出版物標題2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers
發行者Institute of Electrical and Electronics Engineers Inc.
頁面T184-T185
ISBN(電子)9784863485013
DOIs
出版狀態已發佈 - 2015 8月 25
事件Symposium on VLSI Technology, VLSI Technology 2015 - Kyoto, 日本
持續時間: 2015 6月 162015 6月 18

出版系列

名字Digest of Technical Papers - Symposium on VLSI Technology
2015-August
ISSN(列印)0743-1562

其他

其他Symposium on VLSI Technology, VLSI Technology 2015
國家/地區日本
城市Kyoto
期間2015/06/162015/06/18

ASJC Scopus subject areas

  • 電氣與電子工程

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