Low power 1T DRAM/NVM versatile memory featuring steep sub-60-mV/decade operation, fast 20-ns speed, and robust 85°C-extrapolated 1016 endurance

Yu Chien Chiu; Chun Hu Cheng; Chun Yen Chang; Min Hung Lee; Hsiao Hsuan Hsu; Shiang Shiou Yen

doi:10.1109/VLSIT.2015.7223671

Low power 1T DRAM/NVM versatile memory featuring steep sub-60-mV/decade operation, fast 20-ns speed, and robust 85°C-extrapolated 10¹⁶ endurance

Yu Chien Chiu, Chun Hu Cheng, Chun Yen Chang, Min Hung Lee, Hsiao Hsuan Hsu, Shiang Shiou Yen

光電工程學士學位學程

研究成果: 書貢獻/報告類型 › 會議論文篇章

53 引文斯高帕斯（Scopus）

摘要

In this work, we report a one-transistor (1T) versatile memory; the memory transistor characteristics achieve sub-60-mV/dec operation and considerably low off-state leakage of 10^-15 A/μm at a supply voltage below 0.5V. The versatile memory features DRAM/NVM functions of large ΔV_T window of 2.8V, fast 20-ns speed, 10³s retention at 85°C, and long extrapolated 10¹⁶ endurance at 85°C, which show the potential for 3D memory application with severe requirement on both high density and low power consumption.

原文	英語
主出版物標題	2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	T184-T185
ISBN（電子）	9784863485013
DOIs	https://doi.org/10.1109/VLSIT.2015.7223671
出版狀態	已發佈 - 2015 8月 25
事件	Symposium on VLSI Technology, VLSI Technology 2015 - Kyoto, 日本持續時間: 2015 6月 16 → 2015 6月 18

出版系列

名字	Digest of Technical Papers - Symposium on VLSI Technology
卷	2015-August
ISSN（列印）	0743-1562

其他

其他	Symposium on VLSI Technology, VLSI Technology 2015
國家/地區	日本
城市	Kyoto
期間	2015/06/16 → 2015/06/18

ASJC Scopus subject areas

電氣與電子工程

存取文件

10.1109/VLSIT.2015.7223671

其它文件與鏈接

引用此

Chiu, Y. C., Cheng, C. H., Chang, C. Y., Lee, M. H., Hsu, H. H., & Yen, S. S. (2015). Low power 1T DRAM/NVM versatile memory featuring steep sub-60-mV/decade operation, fast 20-ns speed, and robust 85°C-extrapolated 10¹⁶ endurance. 於 2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers (頁 T184-T185). 文章 7223671 (Digest of Technical Papers - Symposium on VLSI Technology; 卷 2015-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.2015.7223671

Low power 1T DRAM/NVM versatile memory featuring steep sub-60-mV/decade operation, fast 20-ns speed, and robust 85°C-extrapolated 10¹⁶ endurance. / Chiu, Yu Chien; Cheng, Chun Hu; Chang, Chun Yen 等.
2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2015. p. T184-T185 7223671 (Digest of Technical Papers - Symposium on VLSI Technology; 卷 2015-August).

研究成果: 書貢獻/報告類型 › 會議論文篇章

Chiu, YC, Cheng, CH, Chang, CY, Lee, MH, Hsu, HH & Yen, SS 2015, Low power 1T DRAM/NVM versatile memory featuring steep sub-60-mV/decade operation, fast 20-ns speed, and robust 85°C-extrapolated 10¹⁶ endurance. 於 2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers., 7223671, Digest of Technical Papers - Symposium on VLSI Technology, 卷 2015-August, Institute of Electrical and Electronics Engineers Inc., 頁 T184-T185, Symposium on VLSI Technology, VLSI Technology 2015, Kyoto, 日本, 2015/06/16. https://doi.org/10.1109/VLSIT.2015.7223671

Chiu YC, Cheng CH, Chang CY, Lee MH, Hsu HH, Yen SS. Low power 1T DRAM/NVM versatile memory featuring steep sub-60-mV/decade operation, fast 20-ns speed, and robust 85°C-extrapolated 10¹⁶ endurance. 於 2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2015. p. T184-T185. 7223671. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSIT.2015.7223671

Chiu, Yu Chien ; Cheng, Chun Hu ; Chang, Chun Yen 等. / Low power 1T DRAM/NVM versatile memory featuring steep sub-60-mV/decade operation, fast 20-ns speed, and robust 85°C-extrapolated 10¹⁶ endurance. 2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2015. 頁 T184-T185 (Digest of Technical Papers - Symposium on VLSI Technology).

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abstract = "In this work, we report a one-transistor (1T) versatile memory; the memory transistor characteristics achieve sub-60-mV/dec operation and considerably low off-state leakage of 10-15 A/μm at a supply voltage below 0.5V. The versatile memory features DRAM/NVM functions of large ΔVT window of 2.8V, fast 20-ns speed, 103s retention at 85°C, and long extrapolated 1016 endurance at 85°C, which show the potential for 3D memory application with severe requirement on both high density and low power consumption.",

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