Low power 1T DRAM/NVM versatile memory featuring steep sub-60-mV/decade operation, fast 20-ns speed, and robust 85°C-extrapolated 1016 endurance

Yu Chien Chiu, Chun-Hu Cheng, Chun Yen Chang, Min-Hung Lee, Hsiao Hsuan Hsu, Shiang Shiou Yen

研究成果: 書貢獻/報告類型會議貢獻

27 引文 (Scopus)

摘要

In this work, we report a one-transistor (1T) versatile memory; the memory transistor characteristics achieve sub-60-mV/dec operation and considerably low off-state leakage of 10-15 A/μm at a supply voltage below 0.5V. The versatile memory features DRAM/NVM functions of large ΔVT window of 2.8V, fast 20-ns speed, 103s retention at 85°C, and long extrapolated 1016 endurance at 85°C, which show the potential for 3D memory application with severe requirement on both high density and low power consumption.

原文英語
主出版物標題2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers
發行者Institute of Electrical and Electronics Engineers Inc.
頁面T184-T185
ISBN(電子)9784863485013
DOIs
出版狀態已發佈 - 2015 八月 25
事件Symposium on VLSI Technology, VLSI Technology 2015 - Kyoto, 日本
持續時間: 2015 六月 162015 六月 18

出版系列

名字Digest of Technical Papers - Symposium on VLSI Technology
2015-August
ISSN(列印)0743-1562

其他

其他Symposium on VLSI Technology, VLSI Technology 2015
國家日本
城市Kyoto
期間15/6/1615/6/18

指紋

Dynamic random access storage
Durability
Data storage equipment
Transistors
Electric power utilization
Electric potential

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

引用此文

Chiu, Y. C., Cheng, C-H., Chang, C. Y., Lee, M-H., Hsu, H. H., & Yen, S. S. (2015). Low power 1T DRAM/NVM versatile memory featuring steep sub-60-mV/decade operation, fast 20-ns speed, and robust 85°C-extrapolated 1016 endurance. 於 2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers (頁 T184-T185). [7223671] (Digest of Technical Papers - Symposium on VLSI Technology; 卷 2015-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.2015.7223671

Low power 1T DRAM/NVM versatile memory featuring steep sub-60-mV/decade operation, fast 20-ns speed, and robust 85°C-extrapolated 1016 endurance. / Chiu, Yu Chien; Cheng, Chun-Hu; Chang, Chun Yen; Lee, Min-Hung; Hsu, Hsiao Hsuan; Yen, Shiang Shiou.

2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2015. p. T184-T185 7223671 (Digest of Technical Papers - Symposium on VLSI Technology; 卷 2015-August).

研究成果: 書貢獻/報告類型會議貢獻

Chiu, YC, Cheng, C-H, Chang, CY, Lee, M-H, Hsu, HH & Yen, SS 2015, Low power 1T DRAM/NVM versatile memory featuring steep sub-60-mV/decade operation, fast 20-ns speed, and robust 85°C-extrapolated 1016 endurance. 於 2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers., 7223671, Digest of Technical Papers - Symposium on VLSI Technology, 卷 2015-August, Institute of Electrical and Electronics Engineers Inc., 頁 T184-T185, Symposium on VLSI Technology, VLSI Technology 2015, Kyoto, 日本, 15/6/16. https://doi.org/10.1109/VLSIT.2015.7223671
Chiu YC, Cheng C-H, Chang CY, Lee M-H, Hsu HH, Yen SS. Low power 1T DRAM/NVM versatile memory featuring steep sub-60-mV/decade operation, fast 20-ns speed, and robust 85°C-extrapolated 1016 endurance. 於 2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2015. p. T184-T185. 7223671. (Digest of Technical Papers - Symposium on VLSI Technology). https://doi.org/10.1109/VLSIT.2015.7223671
Chiu, Yu Chien ; Cheng, Chun-Hu ; Chang, Chun Yen ; Lee, Min-Hung ; Hsu, Hsiao Hsuan ; Yen, Shiang Shiou. / Low power 1T DRAM/NVM versatile memory featuring steep sub-60-mV/decade operation, fast 20-ns speed, and robust 85°C-extrapolated 1016 endurance. 2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2015. 頁 T184-T185 (Digest of Technical Papers - Symposium on VLSI Technology).
@inproceedings{6eae10b6cf2d43c3ae3e1384b7032848,
title = "Low power 1T DRAM/NVM versatile memory featuring steep sub-60-mV/decade operation, fast 20-ns speed, and robust 85°C-extrapolated 1016 endurance",
abstract = "In this work, we report a one-transistor (1T) versatile memory; the memory transistor characteristics achieve sub-60-mV/dec operation and considerably low off-state leakage of 10-15 A/μm at a supply voltage below 0.5V. The versatile memory features DRAM/NVM functions of large ΔVT window of 2.8V, fast 20-ns speed, 103s retention at 85°C, and long extrapolated 1016 endurance at 85°C, which show the potential for 3D memory application with severe requirement on both high density and low power consumption.",
author = "Chiu, {Yu Chien} and Chun-Hu Cheng and Chang, {Chun Yen} and Min-Hung Lee and Hsu, {Hsiao Hsuan} and Yen, {Shiang Shiou}",
year = "2015",
month = "8",
day = "25",
doi = "10.1109/VLSIT.2015.7223671",
language = "English",
series = "Digest of Technical Papers - Symposium on VLSI Technology",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "T184--T185",
booktitle = "2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers",

}

TY - GEN

T1 - Low power 1T DRAM/NVM versatile memory featuring steep sub-60-mV/decade operation, fast 20-ns speed, and robust 85°C-extrapolated 1016 endurance

AU - Chiu, Yu Chien

AU - Cheng, Chun-Hu

AU - Chang, Chun Yen

AU - Lee, Min-Hung

AU - Hsu, Hsiao Hsuan

AU - Yen, Shiang Shiou

PY - 2015/8/25

Y1 - 2015/8/25

N2 - In this work, we report a one-transistor (1T) versatile memory; the memory transistor characteristics achieve sub-60-mV/dec operation and considerably low off-state leakage of 10-15 A/μm at a supply voltage below 0.5V. The versatile memory features DRAM/NVM functions of large ΔVT window of 2.8V, fast 20-ns speed, 103s retention at 85°C, and long extrapolated 1016 endurance at 85°C, which show the potential for 3D memory application with severe requirement on both high density and low power consumption.

AB - In this work, we report a one-transistor (1T) versatile memory; the memory transistor characteristics achieve sub-60-mV/dec operation and considerably low off-state leakage of 10-15 A/μm at a supply voltage below 0.5V. The versatile memory features DRAM/NVM functions of large ΔVT window of 2.8V, fast 20-ns speed, 103s retention at 85°C, and long extrapolated 1016 endurance at 85°C, which show the potential for 3D memory application with severe requirement on both high density and low power consumption.

UR - http://www.scopus.com/inward/record.url?scp=84951078394&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84951078394&partnerID=8YFLogxK

U2 - 10.1109/VLSIT.2015.7223671

DO - 10.1109/VLSIT.2015.7223671

M3 - Conference contribution

AN - SCOPUS:84951078394

T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - T184-T185

BT - 2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers

PB - Institute of Electrical and Electronics Engineers Inc.

ER -