TY - JOUR
T1 - Low-capacitance SCR with waffle layout structure for on-chip ESD protection in RF ICs
AU - Ker, Ming Dou
AU - Lin, Chun Yu
N1 - Funding Information:
The authors would like to thank the Ansoft Corporation, Pittsburgh, PA, for the support of Ansoft Designer/Nexxim for the deembedding calculation. The authors would also like to thank the Editors-in-Chief of this TRANSACTIONS and their reviewers for their valuable suggestions to improve this paper’s manuscript.
Funding Information:
Manuscript received September 1, 2007; revised January 25, 2008. This work was supported by the National Science Council (NSC), Taiwan, R.O.C., under Contract NSC96-2221-E-009-182. The authors are with the Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2008.920176
PY - 2008/5
Y1 - 2008/5
N2 - The silicon-controlled rectifier (SCR) has been used as an effective on-chip electrostatic discharge (ESD) protection device in CMOS technology due to the highest ESD robustness in nanoscale integrated circuits (ICs). In this study, the SCR realized in a waffle layout structure is proposed to improve ESD current distribution efficiency for ESD protection and to reduce the parasitic capacitance. The waffle layout structure of the SCR can achieve smaller parasitic capacitance under the same ESD robustness. With smaller parasitic capacitance, the degradation on RF circuit performance due to ESD protection devices can be reduced. The proposed waffle SCR with low parasitic capacitance is suitable for on-chip ESD protection in RF ICs. Besides, the desired current to trigger on the SCR device with a waffle layout structure and its turn-on time has also been investigated in a silicon chip.
AB - The silicon-controlled rectifier (SCR) has been used as an effective on-chip electrostatic discharge (ESD) protection device in CMOS technology due to the highest ESD robustness in nanoscale integrated circuits (ICs). In this study, the SCR realized in a waffle layout structure is proposed to improve ESD current distribution efficiency for ESD protection and to reduce the parasitic capacitance. The waffle layout structure of the SCR can achieve smaller parasitic capacitance under the same ESD robustness. With smaller parasitic capacitance, the degradation on RF circuit performance due to ESD protection devices can be reduced. The proposed waffle SCR with low parasitic capacitance is suitable for on-chip ESD protection in RF ICs. Besides, the desired current to trigger on the SCR device with a waffle layout structure and its turn-on time has also been investigated in a silicon chip.
KW - Electrostatic discharge (ESD)
KW - RF integrated circuit (RF IC)
KW - Silicon-controlled rectifier (SCR)
UR - http://www.scopus.com/inward/record.url?scp=44049091493&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=44049091493&partnerID=8YFLogxK
U2 - 10.1109/TMTT.2008.920176
DO - 10.1109/TMTT.2008.920176
M3 - Article
AN - SCOPUS:44049091493
SN - 0018-9480
VL - 56
SP - 1286
EP - 1294
JO - IEEE Transactions on Microwave Theory and Techniques
JF - IEEE Transactions on Microwave Theory and Techniques
IS - 5
M1 - 4479882
ER -